From patchwork Fri Feb 28 09:38:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13995996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8548FC282D0 for ; Fri, 28 Feb 2025 09:38:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C956210EC4F; Fri, 28 Feb 2025 09:38:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OkWEmj3J"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id A0F2710EC3F; Fri, 28 Feb 2025 09:38:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740735533; x=1772271533; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I92UHCPO8hLnGHeJAP9YBnqaRydEh+BY3RDpYZlEz20=; b=OkWEmj3Je/1S6BZuY1E7Yu1oqc2rDILNEGqQxFMwXnv5WmzS/6m0m8A8 zeGr6kDh+tmWsnlVIf3zyDfeaHrPfuMGueFUCZ1xHPQq8HhiGKJT34pcV 7+YjS5Wny8Il8rt08nDkO+CQ6p29srwemeVQzypjUiUwejs/CijD5EBup QzeT4RHitG2xk9wv2FkmLyYCR0k6/L+O9W/YjaIWTcXq7CcA4m4xvo7en 9sdLWg6mVH/XLo8i1nQHKJYboKI/MPx8uXF/f31AlByBjf/HsbA4wMrfd 50fywv2NPmKdAaIaL81RLU7EWRi0GgUgOrhdqlnpD799Z6tuII3ezRLXV Q==; X-CSE-ConnectionGUID: PV/7FrZaTq+msgRep2WnRw== X-CSE-MsgGUID: GnxlAZaVTZelQL3X2uWGfg== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="52293102" X-IronPort-AV: E=Sophos;i="6.13,322,1732608000"; d="scan'208";a="52293102" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2025 01:38:53 -0800 X-CSE-ConnectionGUID: jFKXUwcuS8CA4Zr53gxAng== X-CSE-MsgGUID: ag9ZtT3SRkWEWl+R4Fj1qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="154466597" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.23]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2025 01:38:50 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, vinod.govindapillai@intel.com, jani.nikula@intel.com, jani.saarinen@intel.com Subject: [PATCH v10 8/9] drm/i915/fbc: disable FBC if PSR2 selective fetch is enabled Date: Fri, 28 Feb 2025 11:38:01 +0200 Message-ID: <20250228093802.27091-9-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228093802.27091-1-vinod.govindapillai@intel.com> References: <20250228093802.27091-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It is not recommended to have both FBC dirty rect and PSR2 selective fetch be enabled at the same time. Mark FBC as not possible, if PSR2 selective fetch is enabled. v2: fix the condition to disable FBC if PSR2 enabled (Jani) v3: use HAS_FBC_DIRTY_RECT() v4: Update to patch description Bspec: 68881 Reviewed-by: Ville Syrjälä Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ee2d75303e41..5b6a9315fa8f 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1415,9 +1415,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 + * + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot + * coexist. So if PSR2 selective fetch is supported then mark that + * FBC is not supported. + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect */ - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && - !crtc_state->has_panel_replay) { + if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) && + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; }