From patchwork Mon Mar 10 19:59:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ariel D'Alessandro X-Patchwork-Id: 14010588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A159CC282DE for ; Mon, 10 Mar 2025 20:00:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1063010E4DC; Mon, 10 Mar 2025 20:00:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b="HrkY0K1V"; dkim-atps=neutral Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) by gabe.freedesktop.org (Postfix) with ESMTPS id C1D8310E4DC for ; Mon, 10 Mar 2025 20:00:32 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; t=1741636820; cv=none; d=zohomail.com; s=zohoarc; b=Ep1jAyWe1+XXmXUKDfGKdFqzwvvx567SCPi/EfuLlFK1zh0y4LBX0Exk9U5dGmI1gQJUoWg3uPZ0uOcZiTgCPpTGHxgl1usND5ilmo9DT5ATrMJyrpDKaKM/EVOKdFbhpB7fLqwd0G5lHrmYf8dKMFfbI4jLSbHrKAe3ioduwWU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741636820; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ri5NxGP83GAWZRTNAwusSEW6eUICnHU4WNe3YwZobXY=; b=fGPxV/0+GRiJAv1SHqyW9RDRFCRf4N7/wFT/IWpWVnUOGkU+fcyfhBgiOcJXq91mWlq4Ozox9dpp7ZLBc1B9PxOJ9h07SY+PbMB37EwuWjr5PLtWGuRVr7bW5HoGVC/ldA3ztN9E7dasfowC3Q1MPDSjB79/ka4LWwZFPYNUQ48= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=ariel.dalessandro@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1741636820; s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=Ri5NxGP83GAWZRTNAwusSEW6eUICnHU4WNe3YwZobXY=; b=HrkY0K1V0fypJT4eC4spkdxIKpb07lKFGZP7EJJx+FXGftYALB/4BzpES7ozc/xe hyJfrUnyI0M49ueGBJZbTvucN82b3KrQNG7DkFWFwR6cXNb3euNo6PPIPRTMEa1uUE9 cyZBgbL+Kg+WTuVUQrLQhx7IGQeIoXSMmBFoEe8k= Received: by mx.zohomail.com with SMTPS id 1741636818884184.34015520872072; Mon, 10 Mar 2025 13:00:18 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, Ariel D'Alessandro Subject: [PATCH v1 6/6] drm/panfrost: Set HW_FEATURE_AARCH64_MMU feature flag on Bifrost models Date: Mon, 10 Mar 2025 16:59:21 -0300 Message-ID: <20250310195921.157511-7-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250310195921.157511-1-ariel.dalessandro@collabora.com> References: <20250310195921.157511-1-ariel.dalessandro@collabora.com> MIME-Version: 1.0 X-ZohoMailClient: External X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Set this feature flag on all Mali Bifrost platforms as the MMU supports AARCH64 4K page table format. Signed-off-by: Ariel D'Alessandro Reviewed-by: Boris Brezillon --- drivers/gpu/drm/panfrost/panfrost_features.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_features.h b/drivers/gpu/drm/panfrost/panfrost_features.h index 7ed0cd3ea2d4c..52f9d69f6db9d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_features.h +++ b/drivers/gpu/drm/panfrost/panfrost_features.h @@ -54,6 +54,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \ BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \ BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) #define hw_features_g72 (\ @@ -64,6 +65,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \ BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) #define hw_features_g51 hw_features_g72 @@ -77,6 +79,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \ BIT_ULL(HW_FEATURE_IDVS_GROUP_SIZE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) #define hw_features_g76 (\