diff mbox series

[v2,5/6] drm/i915/gt/uc: Use FIRST_CCS() helper for one-time CCS operations

Message ID 20250326234005.1574688-6-andi.shyti@linux.intel.com (mailing list archive)
State New
Headers show
Series Remove I915_ENGINE_FIRST_RENDER_COMPUTE | expand

Commit Message

Andi Shyti March 26, 2025, 11:40 p.m. UTC 
From: Andi Shyti <andi.shyti@intel.com>

Replace checks for I915_ENGINE_FIRST_RENDER_COMPUTE combined
with CCS_MASK() with the FIRST_CCS() helper. This improves
readability and ensures that certain CCS-specific actions, such
as enabling GEN12_RCU_MODE and calling xehp_enable_ccs_engines(),
are performed only once, on the first CCS engine encountered.

This is particularly relevant for platforms like DG2, which
support multiple CCS engines.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c        | 3 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 46fabbfc775e..bf1686af29e7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -392,8 +392,7 @@  static int guc_mmio_regset_init(struct temp_regset *regset,
 	ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false);
 	ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false);
 
-	if ((engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) &&
-	    CCS_MASK(engine->gt))
+	if (FIRST_CCS(engine))
 		ret |= GUC_MMIO_REG_ADD(gt, regset, GEN12_RCU_MODE, true);
 
 	/*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f8cb7c630d5b..18545196c9f4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4422,7 +4422,7 @@  static int guc_resume(struct intel_engine_cs *engine)
 	setup_hwsp(engine);
 	start_engine(engine);
 
-	if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
+	if (FIRST_CCS(engine))
 		xehp_enable_ccs_engines(engine);
 
 	return 0;