| Message ID | 20250328-asyn-v11-3-a50d13bfea0d@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Expose modifiers/formats supported by async flips | expand |
On Fri, Mar 28, 2025 at 09:26:22PM +0530, Arun R Murthy wrote: > The function intel_plane_can_async_flip() checks for async supported > modifier, add format support check also in the same function. > > Note: on ADL the surface base addr is required to be 16k aligned and if > not might generate DMAR and GGTT faults leading to glitches. What we want to highlight is that this *changes* the alignment from 16K to 4K for planar formats on ADL. > > v11: Move filtering Indexed 8bit to a separate patch (Ville) > v12: correct the commit msg and remove unwanted debug print (Ville) > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> > --- > drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_atomic_plane.c | 6 +++++- > drivers/gpu/drm/i915/display/intel_atomic_plane.h | 3 ++- > drivers/gpu/drm/i915/display/intel_display.c | 14 ++++---------- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- > 5 files changed, 14 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c > index 5e8344fdfc28a311dc0632bb848a0e08f9e6c6d2..20c47de6d8bfd1d8ddafae02ed68370df799e22b 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > @@ -828,7 +828,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, > { > struct intel_display *display = to_intel_display(plane); > > - if (intel_plane_can_async_flip(plane, fb->modifier)) > + if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) > return 256 * 1024; > > /* FIXME undocumented so not sure what's actually needed */ > @@ -852,7 +852,7 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, > { > struct intel_display *display = to_intel_display(plane); > > - if (intel_plane_can_async_flip(plane, fb->modifier)) > + if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) > return 256 * 1024; > > if (intel_scanout_needs_vtd_wa(display)) > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c > index 7276179df878658b7053fe6d8dc37b69f19625e3..1ec730047759cb22b3e0fabfd2eaddbc1bc865af 100644 > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c > @@ -174,8 +174,12 @@ bool intel_plane_needs_physical(struct intel_plane *plane) > DISPLAY_INFO(display)->cursor_needs_physical; > } > > -bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier) > +bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, > + u64 modifier) > { > + if (intel_format_info_is_yuv_semiplanar(drm_format_info(format), modifier)) > + return false; > + > return plane->can_async_flip && plane->can_async_flip(modifier); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h > index 6efac923dcbc757e6f68564cbef2919c920f13cb..772a12aa9c6997d77b9393f964e91f3e8747d149 100644 > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h > @@ -21,7 +21,8 @@ enum plane_id; > > struct intel_plane * > intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id); > -bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier); > +bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, > + u64 modifier); > unsigned int intel_adjusted_rate(const struct drm_rect *src, > const struct drm_rect *dst, > unsigned int rate); > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 103173836abf9ea3a9094d2726d3dfbc94023ea6..542fe21a1f32588a8f4d9e133475b15c4132c4c9 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5998,22 +5998,16 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in > if (!plane->async_flip) > continue; > > - if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) { > + if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format, > + new_plane_state->hw.fb->modifier)) { > drm_dbg_kms(display->drm, > - "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", > + "[PLANE:%d:%s] Format %p4cc Modifier 0x%llx does not support async flip\n", I would make that "... pixel format %p4cc / modifier 0x%llx ..." to be consistent with some existing printk in intel_fb.c. Apart from those lgtm Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > plane->base.base.id, plane->base.name, > + &new_plane_state->hw.fb->format->format, > new_plane_state->hw.fb->modifier); > return -EINVAL; > } > > - if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format, > - new_plane_state->hw.fb->modifier)) { > - drm_dbg_kms(display->drm, > - "[PLANE:%d:%s] Planar formats do not support async flips\n", > - plane->base.base.id, plane->base.name); > - return -EINVAL; > - } > - > /* > * We turn the first async flip request into a sync flip > * so that we can reconfigure the plane (eg. change modifier). > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 8739195aba696d13b30e1b978c8b2bb5e188119b..8f6170a5c108a000582f3415f78bad279254d8cf 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -601,7 +601,7 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, > * Figure out what's going on here... > */ > if (display->platform.alderlake_p && > - intel_plane_can_async_flip(plane, fb->modifier)) > + intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) > return mult * 16 * 1024; > > switch (fb->modifier) { > > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 5e8344fdfc28a311dc0632bb848a0e08f9e6c6d2..20c47de6d8bfd1d8ddafae02ed68370df799e22b 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -828,7 +828,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); - if (intel_plane_can_async_flip(plane, fb->modifier)) + if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) return 256 * 1024; /* FIXME undocumented so not sure what's actually needed */ @@ -852,7 +852,7 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); - if (intel_plane_can_async_flip(plane, fb->modifier)) + if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) return 256 * 1024; if (intel_scanout_needs_vtd_wa(display)) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 7276179df878658b7053fe6d8dc37b69f19625e3..1ec730047759cb22b3e0fabfd2eaddbc1bc865af 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -174,8 +174,12 @@ bool intel_plane_needs_physical(struct intel_plane *plane) DISPLAY_INFO(display)->cursor_needs_physical; } -bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier) +bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, + u64 modifier) { + if (intel_format_info_is_yuv_semiplanar(drm_format_info(format), modifier)) + return false; + return plane->can_async_flip && plane->can_async_flip(modifier); } diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index 6efac923dcbc757e6f68564cbef2919c920f13cb..772a12aa9c6997d77b9393f964e91f3e8747d149 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -21,7 +21,8 @@ enum plane_id; struct intel_plane * intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id); -bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier); +bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, + u64 modifier); unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, unsigned int rate); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 103173836abf9ea3a9094d2726d3dfbc94023ea6..542fe21a1f32588a8f4d9e133475b15c4132c4c9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5998,22 +5998,16 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (!plane->async_flip) continue; - if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) { + if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format, + new_plane_state->hw.fb->modifier)) { drm_dbg_kms(display->drm, - "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", + "[PLANE:%d:%s] Format %p4cc Modifier 0x%llx does not support async flip\n", plane->base.base.id, plane->base.name, + &new_plane_state->hw.fb->format->format, new_plane_state->hw.fb->modifier); return -EINVAL; } - if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format, - new_plane_state->hw.fb->modifier)) { - drm_dbg_kms(display->drm, - "[PLANE:%d:%s] Planar formats do not support async flips\n", - plane->base.base.id, plane->base.name); - return -EINVAL; - } - /* * We turn the first async flip request into a sync flip * so that we can reconfigure the plane (eg. change modifier). diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 8739195aba696d13b30e1b978c8b2bb5e188119b..8f6170a5c108a000582f3415f78bad279254d8cf 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -601,7 +601,7 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, * Figure out what's going on here... */ if (display->platform.alderlake_p && - intel_plane_can_async_flip(plane, fb->modifier)) + intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) return mult * 16 * 1024; switch (fb->modifier) {
The function intel_plane_can_async_flip() checks for async supported modifier, add format support check also in the same function. Note: on ADL the surface base addr is required to be 16k aligned and if not might generate DMAR and GGTT faults leading to glitches. v11: Move filtering Indexed 8bit to a separate patch (Ville) v12: correct the commit msg and remove unwanted debug print (Ville) Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 6 +++++- drivers/gpu/drm/i915/display/intel_atomic_plane.h | 3 ++- drivers/gpu/drm/i915/display/intel_display.c | 14 ++++---------- drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- 5 files changed, 14 insertions(+), 15 deletions(-)