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Sun, 30 Mar 2025 10:31:50 -0700 (PDT) Received: from localhost ([2a00:23c8:b70a:ae01:9cf7:b69:fc50:980f]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-39c0b66285bsm8937562f8f.21.2025.03.30.10.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Mar 2025 10:31:50 -0700 (PDT) From: Christopher Obbard Date: Sun, 30 Mar 2025 18:31:43 +0100 Subject: [PATCH v4] drm/dp: clamp PWM bit count to advertised MIN and MAX capabilities MIME-Version: 1.0 Message-Id: <20250330-wip-obbardc-qcom-t14s-oled-panel-brightness-v4-1-85ef0991bdf8@linaro.org> X-B4-Tracking: v=1; b=H4sIAP5/6WcC/53NQQ6CMBCF4auQrh0ztFDQlfcwLgodYRJssSWoI dxdYKVLXb63+P5JRApMURyTSQQaObJ3y8h2iahb4xoCtssWEmWOShbw4B58VZlga7jX/gZDmkX wHVnojaMOqsBNOziKETKUWOq80nmJYhH7QFd+brXzZdktx8GH1xYf5fr+1xklpJBqWysiRFnoU 8fOBL/3oRFraFQfuMLfcLXiuS4xtYfClOYLn+f5DcePISVEAQAA X-Change-ID: 20250327-wip-obbardc-qcom-t14s-oled-panel-brightness-4020865b6580 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Dmitry Baryshkov Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Johan Hovold , Rui Miguel Silva , Abel Vesa , Christopher Obbard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=F18BDC8B6C25F90AA23D5174634DC4F0687046F8 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" According to the eDP specification (VESA Embedded DisplayPort Standard v1.4b, Section 3.3.10.2), if the value of DP_EDP_PWMGEN_BIT_COUNT is less than DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, the sink is required to use the MIN value as the effective PWM bit count. This commit updates the logic to clamp the reported DP_EDP_PWMGEN_BIT_COUNT to the range defined by DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN and _CAP_MAX. As part of this change, the behavior is modified such that reading _CAP_MIN and _CAP_MAX registers is now required to succeed. Before reading these registers was optional. This ensures correct handling of eDP panels that report a zero PWM bit count but still provide valid non-zero MIN and MAX capability values. Without this clamping, brightness values may be interpreted incorrectly, leading to a dim or non-functional backlight. For example, the Samsung ATNA40YK20 OLED panel used in the Lenovo ThinkPad T14s Gen6 (Snapdragon) reports a PWM bit count of 0, but supports AUX backlight control and declares a valid 11-bit range. Clamping ensures brightness scaling works as intended on such panels. Co-developed-by: Rui Miguel Silva Signed-off-by: Rui Miguel Silva Signed-off-by: Christopher Obbard --- Changes in v4: - Remove unrelated whitespace changes. - Remove unrelated commit change. - Add note to commit message about changing read of PWMGEN_BIT_COUNT_CAP_MIN and _CAP__MAX from optional to required. - Link to v3: https://lore.kernel.org/r/20250330-wip-obbardc-qcom-t14s-oled-panel-brightness-v3-1-156801d97a8a@linaro.org Changes in v3: - Properly rebase patch on top of latest version of drm-misc-next. - Make patch more generic by clamping PWM bit count to advertised MIN and MAX capabilities (suggested by Dmitry). - Link to v2: https://lore.kernel.org/r/20250327-wip-obbardc-qcom-t14s-oled-panel-brightness-v2-1-16dc3ee00276@linaro.org Changes in v2: - Split backlight brightness patch from T14s OLED enablement series. - Use PWMGEN_CAP_MIN rather than MAX (Dmitry). - Rework commit message to reference eDP spec. - Rebase on drm-misc-next. - Link to v1: https://lore.kernel.org/all/20250325-wip-obbardc-qcom-t14s-oled-panel-v2-4-e9bc7c9d30cc@linaro.org/ --- drivers/gpu/drm/display/drm_dp_helper.c | 42 +++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 15 deletions(-) --- base-commit: 4c4d9b7b6c6e676eca22585139aba5f03de74b90 change-id: 20250327-wip-obbardc-qcom-t14s-oled-panel-brightness-4020865b6580 Best regards, diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index e2439c8a7fefe116b04aaa689b557e2387b05540..b5c8a75d036b5d65262417de363409e3ff3f4560 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -4035,6 +4036,32 @@ drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_inf } pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + + ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); + if (ret != 1) { + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", + aux->name, ret); + return -ENODEV; + } + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + + ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); + if (ret != 1) { + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", + aux->name, ret); + return -ENODEV; + } + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + + /* + * Per VESA eDP Spec v1.4b, section 3.3.10.2: + * If DP_EDP_PWMGEN_BIT_COUNT is less than DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, + * the sink must use the MIN value as the effective PWM bit count. + * Clamp the reported value to the [MIN, MAX] capability range to ensure + * correct brightness scaling on compliant eDP panels. + */ + pn = clamp(pn, pn_min, pn_max); + bl->max = (1 << pn) - 1; if (!driver_pwm_freq_hz) return 0; @@ -4061,21 +4088,6 @@ drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_inf * - FxP is within 25% of desired value. * Note: 25% is arbitrary value and may need some tweak. */ - ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); - if (ret < 0) { - drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", - aux->name, ret); - return 0; - } - ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); - if (ret < 0) { - drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", - aux->name, ret); - return 0; - } - pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; - pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; - /* Ensure frequency is within 25% of desired value */ fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);