diff mbox

i915 SSC Patch

Message ID 4E32ADC7.3080002@codethink.co.uk (mailing list archive)
State New, archived
Headers show

Commit Message

Ben Brewer July 29, 2011, 12:55 p.m. UTC 
I've added a global SSC (Spread Spectrum Clock) parameter to the i915 
driver, since having SSC enabled breaks (distorts) VGA output on some 
Core i5/i7 chips (see https://bugs.freedesktop.org/show_bug.cgi?id=38750).
SSC is still enabled by default so the behaviour won't change but 
setting the global_use_ssc parameter will turn this feature off and 
allow affected devices to function correctly (notably the Dell Vostro 3300).

Numerous people have tested this and reported it working (as seen in the 
bug report thread) which isn't surprising considering it's a basic 
modification of Chris Wilsons work.

Any comments, or anybody willing to include this patch?

Thanks,
Ben Brewer (CodeThink)

Comments

Keith Packard July 29, 2011, 6:45 p.m. UTC | #1 
On Fri, 29 Jul 2011 13:55:35 +0100, Ben Brewer <ben.brewer@codethink.co.uk> wrote:

> I've added a global SSC (Spread Spectrum Clock) parameter to the i915 
> driver, since having SSC enabled breaks (distorts) VGA output on some 
> Core i5/i7 chips (see https://bugs.freedesktop.org/show_bug.cgi?id=38750).
> SSC is still enabled by default so the behaviour won't change but 
> setting the global_use_ssc parameter will turn this feature off and 
> allow affected devices to function correctly (notably the Dell Vostro
> 3300).

The question I have is why is SSC enabled on the VGA output at all? I
don't see any way VGA could ever tolerate it.
Chris Wilson July 29, 2011, 7:02 p.m. UTC | #2 
On Fri, 29 Jul 2011 11:45:28 -0700, Keith Packard <keithp@keithp.com> wrote:
Non-text part: multipart/signed
> On Fri, 29 Jul 2011 13:55:35 +0100, Ben Brewer <ben.brewer@codethink.co.uk> wrote:
> 
> > I've added a global SSC (Spread Spectrum Clock) parameter to the i915 
> > driver, since having SSC enabled breaks (distorts) VGA output on some 
> > Core i5/i7 chips (see https://bugs.freedesktop.org/show_bug.cgi?id=38750).
> > SSC is still enabled by default so the behaviour won't change but 
> > setting the global_use_ssc parameter will turn this feature off and 
> > allow affected devices to function correctly (notably the Dell Vostro
> > 3300).
> 
> The question I have is why is SSC enabled on the VGA output at all? I
> don't see any way VGA could ever tolerate it.

It's not meant to be and it causes havoc, from wavy/blurry output to no
sync. The other part of the patch on that bug was to walk the crtcs and
turn off SSC on the shared refclk if any output could not handle SSC. At
that point, an objection was raised that we shouldn't even be touching
the refclk if any output was currently being driven from it.
-Chris
Keith Packard July 29, 2011, 9:18 p.m. UTC | #3 
On Fri, 29 Jul 2011 20:02:27 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:

> It's not meant to be and it causes havoc, from wavy/blurry output to no
> sync. The other part of the patch on that bug was to walk the crtcs and
> turn off SSC on the shared refclk if any output could not handle SSC. At
> that point, an objection was raised that we shouldn't even be touching
> the refclk if any output was currently being driven from it.

So the correct fix is to turn off everything, disable SSC and turn
everything back on? That seems tedious, but not impossible (just DPMS
off the world, then DPMS everything back on...).
Gene Heskett July 29, 2011, 10:01 p.m. UTC | #4 
On Friday, July 29, 2011, Keith Packard wrote:
>On Fri, 29 Jul 2011 13:55:35 +0100, Ben Brewer 
<ben.brewer@codethink.co.uk> wrote:
>> I've added a global SSC (Spread Spectrum Clock) parameter to the i915
>> driver, since having SSC enabled breaks (distorts) VGA output on some
>> Core i5/i7 chips (see
>> https://bugs.freedesktop.org/show_bug.cgi?id=38750). SSC is still
>> enabled by default so the behaviour won't change but setting the
>> global_use_ssc parameter will turn this feature off and allow affected
>> devices to function correctly (notably the Dell Vostro 3300).
>
>The question I have is why is SSC enabled on the VGA output at all? I
>don't see any way VGA could ever tolerate it.

Something does not make sense here Keith, so I'm with you, and my 
background is from about 60 years in tv maintenance and 45 in broadcasting.

A pure digital output, where its a high speed serial transfer of bytes to 
the monitor, is generally not going to be sensitive the any SS used unless 
the baud rate slams around too much on a byte to byte basis.  Since SS is 
generally just a few percent, even that should not be a problem.  But 
feeding analog signals up a video cable to a vga monitor, and the pixel 
time is wobbling by 2 to 5% and you won't have much of a viewable image 
left.  The analog signals, vga etc, needs their own video clock, a dead 
stable one.

We used to spend $10k-30k$ just so we could take the signal from a 
mechanically unstable vcr that only cost us $10k, and make it stable enough 
to work on your home tv's without the top of the pix waving around like 
hurricane Katrina was in the neighborhood.

Hardware design error in the Dell?

Cheers, gene
Keith Packard July 29, 2011, 10:18 p.m. UTC | #5 
On Fri, 29 Jul 2011 18:01:39 -0400, Gene Heskett <gene.heskett@gmail.com> wrote:
> On Friday, July 29, 2011, Keith Packard wrote:
> >On Fri, 29 Jul 2011 13:55:35 +0100, Ben Brewer 
> <ben.brewer@codethink.co.uk> wrote:
> >> I've added a global SSC (Spread Spectrum Clock) parameter to the i915
> >> driver, since having SSC enabled breaks (distorts) VGA output on some
> >> Core i5/i7 chips (see
> >> https://bugs.freedesktop.org/show_bug.cgi?id=38750). SSC is still
> >> enabled by default so the behaviour won't change but setting the
> >> global_use_ssc parameter will turn this feature off and allow affected
> >> devices to function correctly (notably the Dell Vostro 3300).
> >
> >The question I have is why is SSC enabled on the VGA output at all? I
> >don't see any way VGA could ever tolerate it.
> 
> Something does not make sense here Keith, so I'm with you, and my 
> background is from about 60 years in tv maintenance and 45 in
> broadcasting.

Right, I think the basic problem is that we aren't switching SSC on and
off based on whether there's an output which can't tolerate it. Making
this user-configurable doesn't make any sense, it clearly needs to be
done in the driver automatically, based on whether there's an analog
output running (VGA or TV).

> Hardware design error in the Dell?

Nope, just a driver bug :-)
diff mbox

Patch

diff -uNr linux-2.6.38/drivers/gpu/drm/i915/i915_drv.c linux-2.6.38-nossc/drivers/gpu/drm/i915/i915_drv.c
--- linux-2.6.38/drivers/gpu/drm/i915/i915_drv.c	2011-03-15 01:20:32.000000000 +0000
+++ linux-2.6.38-nossc/drivers/gpu/drm/i915/i915_drv.c	2011-07-26 15:06:34.762058717 +0100
@@ -55,7 +55,10 @@ 
 unsigned int i915_lvds_downclock = 0;
 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
 
-unsigned int i915_panel_use_ssc = 1;
+unsigned int i915_use_ssc = 1;
+module_param_named(global_use_ssc, i915_use_ssc, int, 0600);
+
+unsigned int i915_panel_use_ssc = 1;
 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
 
 bool i915_try_reset = true;
diff -uNr linux-2.6.38/drivers/gpu/drm/i915/i915_drv.h linux-2.6.38-nossc/drivers/gpu/drm/i915/i915_drv.h
--- linux-2.6.38/drivers/gpu/drm/i915/i915_drv.h	2011-03-15 01:20:32.000000000 +0000
+++ linux-2.6.38-nossc/drivers/gpu/drm/i915/i915_drv.h	2011-07-26 13:50:31.198058201 +0100
@@ -344,6 +344,7 @@ 
 	unsigned int lvds_vbt:1;
 	unsigned int int_crt_support:1;
 	unsigned int lvds_use_ssc:1;
+	unsigned int display_clock_mode:1;
 	int lvds_ssc_freq;
 	struct {
 		int rate;
@@ -958,6 +959,7 @@ 
 extern unsigned int i915_powersave;
 extern unsigned int i915_semaphores;
 extern unsigned int i915_lvds_downclock;
+extern unsigned int i915_use_ssc;
 extern unsigned int i915_panel_use_ssc;
 extern unsigned int i915_enable_rc6;
 
diff -uNr linux-2.6.38/drivers/gpu/drm/i915/intel_bios.c linux-2.6.38-nossc/drivers/gpu/drm/i915/intel_bios.c
--- linux-2.6.38/drivers/gpu/drm/i915/intel_bios.c	2011-03-15 01:20:32.000000000 +0000
+++ linux-2.6.38-nossc/drivers/gpu/drm/i915/intel_bios.c	2011-07-20 12:53:52.281036594 +0100
@@ -270,6 +270,8 @@ 
 			dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 120;
 		else
 			dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
+
+		dev_priv->display_clock_mode = general->display_clock_mode;
 	}
 }
 
diff -uNr linux-2.6.38/drivers/gpu/drm/i915/intel_bios.h linux-2.6.38-nossc/drivers/gpu/drm/i915/intel_bios.h
--- linux-2.6.38/drivers/gpu/drm/i915/intel_bios.h	2011-03-15 01:20:32.000000000 +0000
+++ linux-2.6.38-nossc/drivers/gpu/drm/i915/intel_bios.h	2011-07-20 12:52:50.309036565 +0100
@@ -120,7 +120,9 @@ 
 	u8 ssc_freq:1;
 	u8 enable_lfp_on_override:1;
 	u8 disable_ssc_ddt:1;
-	u8 rsvd8:3; /* finish byte */
+	u8 rsvd7:1;
+	u8 display_clock_mode:1;
+	u8 rsvd8:1; /* finish byte */
 
         /* bits 3 */
 	u8 disable_smooth_vision:1;
diff -uNr linux-2.6.38/drivers/gpu/drm/i915/intel_display.c linux-2.6.38-nossc/drivers/gpu/drm/i915/intel_display.c
--- linux-2.6.38/drivers/gpu/drm/i915/intel_display.c	2011-07-25 10:12:09.904820505 +0100
+++ linux-2.6.38-nossc/drivers/gpu/drm/i915/intel_display.c	2011-07-26 14:05:07.298058301 +0100
@@ -3924,7 +3924,7 @@ 
 
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
+	return dev_priv->lvds_use_ssc && i915_panel_use_ssc && i915_use_ssc;
 }
 
 static int intel_crtc_mode_set(struct drm_crtc *crtc,
@@ -4153,39 +4153,59 @@ 
 	 */
 	if (HAS_PCH_SPLIT(dev)) {
 		temp = I915_READ(PCH_DREF_CONTROL);
-		/* Always enable nonspread source */
 		temp &= ~DREF_NONSPREAD_SOURCE_MASK;
-		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
 		temp &= ~DREF_SSC_SOURCE_MASK;
-		temp |= DREF_SSC_SOURCE_ENABLE;
+		if (i915_use_ssc) {
+			/* Always enable nonspread source */
+			temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+			temp |= DREF_SSC_SOURCE_ENABLE;
+		} else {
+			temp &= ~DREF_SSC1_ENABLE;
+			temp &= ~DREF_SSC4_ENABLE;
+			temp &= ~DREF_SUPERSPREAD_SOURCE_ENABLE;
+			temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+		}
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 
-		if (has_edp_encoder) {
-			if (intel_panel_use_ssc(dev_priv)) {
-				temp |= DREF_SSC1_ENABLE;
+		if (i915_use_ssc) {
+			if (has_edp_encoder) {
+				if (intel_panel_use_ssc(dev_priv)) {
+					temp |= DREF_SSC1_ENABLE;
+					I915_WRITE(PCH_DREF_CONTROL, temp);
+					POSTING_READ(PCH_DREF_CONTROL);
+					udelay(200);
+				}
+				temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+				
+				/* Enable CPU source on attached eDP */
+				if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+					if (intel_panel_use_ssc(dev_priv))
+						temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+					else
+						temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+				} else {
+					/* Enable SSC on PCH eDP if needed */
+					if (intel_panel_use_ssc(dev_priv)) {
+						DRM_ERROR("enabling SSC on PCH\n");
+						temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
+					}
+				}
 				I915_WRITE(PCH_DREF_CONTROL, temp);
-
 				POSTING_READ(PCH_DREF_CONTROL);
 				udelay(200);
 			}
-			temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+		} else {
+			if (dev_priv->display_clock_mode)
+				temp |= DREF_NONSPREAD_CK505_ENABLE;
+			else
+				temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+			if (has_edp_encoder &&
+				!intel_encoder_is_pch_edp(&has_edp_encoder->base))
+				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
 
-			/* Enable CPU source on CPU attached eDP */
-			if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
-				if (intel_panel_use_ssc(dev_priv))
-					temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
-				else
-					temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
-			} else {
-				/* Enable SSC on PCH eDP if needed */
-				if (intel_panel_use_ssc(dev_priv)) {
-					DRM_ERROR("enabling SSC on PCH\n");
-					temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
-				}
-			}
 			I915_WRITE(PCH_DREF_CONTROL, temp);
 			POSTING_READ(PCH_DREF_CONTROL);
 			udelay(200);