| Message ID | 4b5d243d33433f83874359794b796d4228574714.1524044917.git.sean.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 2018-04-18 at 20:18 -0700, Stephen Boyd wrote: > Quoting sean.wang@mediatek.com (2018-04-18 03:24:54) > > From: Sean Wang <sean.wang@mediatek.com> > > > > Add bindings to g3dsys providing necessary clock and reset control to > > Mali-450. > > > > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > > --- > > .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++ > > Why isn't this under bindings/clock/ ? > Tons of bindings for clock controller have been present at binding/arm/mediatek. g3dsys just have a follow-up to them. It's worth another patch moving them all from bindings/arm/mediatek/ to bindings/clock/mediatek. what's your opinion for either doing it prior to g3dsys binding being added or doing it in the future ? > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Quoting Sean Wang (2018-04-18 20:50:02) > On Wed, 2018-04-18 at 20:18 -0700, Stephen Boyd wrote: > > Quoting sean.wang@mediatek.com (2018-04-18 03:24:54) > > > From: Sean Wang <sean.wang@mediatek.com> > > > > > > Add bindings to g3dsys providing necessary clock and reset control to > > > Mali-450. > > > > > > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > > > --- > > > .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++ > > > > Why isn't this under bindings/clock/ ? > > > > Tons of bindings for clock controller have been present at > binding/arm/mediatek. g3dsys just have a follow-up to them. > > It's worth another patch moving them all from bindings/arm/mediatek/ to > bindings/clock/mediatek. > > what's your opinion for either doing it prior to g3dsys binding being > added or doing it in the future ? > Doing it at a later time is fine. Just wondering why they're all getting dumped into the arm/ directory.
On Wed, Apr 18, 2018 at 06:24:54PM +0800, sean.wang@mediatek.com wrote: > From: Sean Wang <sean.wang@mediatek.com> > > Add bindings to g3dsys providing necessary clock and reset control to > Mali-450. > > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > --- > .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > new file mode 100644 > index 0000000..ff2d70c > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > @@ -0,0 +1,30 @@ > +MediaTek g3dsys controller > +============================ > + > +The MediaTek g3dsys controller provides various clocks and reset controller to > +the GPU. > + > +Required Properties: > + > +- compatible: Should be: > + - "mediatek,mt2701-g3dsys", "syscon": > + for MT2701 SoC > + - "mediatek,mt7623-ethsys", "mediatek,mt2701-g3dsys", "syscon": > + for MT7623 SoC ethsys? > +- #clock-cells: Must be 1 > +- #reset-cells: Must be 1 > + > +The ethsys controller uses the common clk binding from > +Documentation/devicetree/bindings/clock/clock-bindings.txt > +The available clocks are defined in dt-bindings/clock/mt*-clk.h. > + > +Example: > + > +g3dsys: clock-controller@13000000 { > + compatible = "mediatek,mt7623-g3dsys", > + "mediatek,mt2701-g3dsys", > + "syscon"; > + reg = <0 0x13000000 0 0x200>; > + #clock-cells = <1>; > + #reset-cells = <1>; > +}; > -- > 2.7.4 >
On Tue, 2018-04-24 at 09:39 -0500, Rob Herring wrote: > On Wed, Apr 18, 2018 at 06:24:54PM +0800, sean.wang@mediatek.com wrote: > > From: Sean Wang <sean.wang@mediatek.com> > > > > Add bindings to g3dsys providing necessary clock and reset control to > > Mali-450. > > > > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > > --- > > .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > > > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > > new file mode 100644 > > index 0000000..ff2d70c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt > > @@ -0,0 +1,30 @@ > > +MediaTek g3dsys controller > > +============================ > > + > > +The MediaTek g3dsys controller provides various clocks and reset controller to > > +the GPU. > > + > > +Required Properties: > > + > > +- compatible: Should be: > > + - "mediatek,mt2701-g3dsys", "syscon": > > + for MT2701 SoC > > + - "mediatek,mt7623-ethsys", "mediatek,mt2701-g3dsys", "syscon": > > + for MT7623 SoC > > ethsys? > thanks! I'll also fix it up in the next version. > > +- #clock-cells: Must be 1 > > +- #reset-cells: Must be 1 > > + > > +The ethsys controller uses the common clk binding from > > +Documentation/devicetree/bindings/clock/clock-bindings.txt > > +The available clocks are defined in dt-bindings/clock/mt*-clk.h. > > + > > +Example: > > + > > +g3dsys: clock-controller@13000000 { > > + compatible = "mediatek,mt7623-g3dsys", > > + "mediatek,mt2701-g3dsys", > > + "syscon"; > > + reg = <0 0x13000000 0 0x200>; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > +}; > > -- > > 2.7.4 > >
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt new file mode 100644 index 0000000..ff2d70c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt @@ -0,0 +1,30 @@ +MediaTek g3dsys controller +============================ + +The MediaTek g3dsys controller provides various clocks and reset controller to +the GPU. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt2701-g3dsys", "syscon": + for MT2701 SoC + - "mediatek,mt7623-ethsys", "mediatek,mt2701-g3dsys", "syscon": + for MT7623 SoC +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The ethsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +g3dsys: clock-controller@13000000 { + compatible = "mediatek,mt7623-g3dsys", + "mediatek,mt2701-g3dsys", + "syscon"; + reg = <0 0x13000000 0 0x200>; + #clock-cells = <1>; + #reset-cells = <1>; +};