From patchwork Wed Aug 12 00:33:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Kleiner X-Patchwork-Id: 6995201 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6AFEAC05AC for ; Wed, 12 Aug 2015 00:33:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 72C9E206D0 for ; Wed, 12 Aug 2015 00:33:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 347B1206CC for ; Wed, 12 Aug 2015 00:33:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A6816E0C0; Tue, 11 Aug 2015 17:33:47 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wi0-f173.google.com (mail-wi0-f173.google.com [209.85.212.173]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C6A66E0C0; Tue, 11 Aug 2015 17:33:45 -0700 (PDT) Received: by wicne3 with SMTP id ne3so80934731wic.0; Tue, 11 Aug 2015 17:33:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=ss8moWk0F39hBRlIx8GgvtKqqpvEV8SB0mEZ+vxQWNQ=; b=rJRDSqP/LY3XSkRAi8A0KqgfWgCyI/dRFk6P+Iel7FMk8QDZXlpm5hem/u5gDR+dZ6 p4gKbU7qufd3GIHM5qO48vqMh84w2t85HVtb24DytMuSbVQeyDhsbR83Yr1AK05QDeda R6Ce6rJwANwhe+hKiVebECSoPoRbcOB3luZSBrJt3iuDPo0bEvJeBBLK6UUDDh07rYcP bJkf2vpndQr8yq83geVlW9NreQ5MH7Vey1euOc2Hc/8GXKo9KxM/sHw56F3sAaMVtTK1 PHBrGN7WTf9idHv7kNEbOKqmQ2Mz7v6xs0JV0TK4M8uPkf1oqOcMAB4jGC3MOxtN4ajZ L50g== X-Received: by 10.194.81.137 with SMTP id a9mr65909012wjy.155.1439339623673; Tue, 11 Aug 2015 17:33:43 -0700 (PDT) Received: from [192.168.178.25] (x5f71771e.dyn.telefonica.de. [95.113.119.30]) by smtp.gmail.com with ESMTPSA id r19sm5698075wib.7.2015.08.11.17.33.42 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Aug 2015 17:33:42 -0700 (PDT) Message-ID: <55CA9464.3030204@gmail.com> Date: Wed, 12 Aug 2015 02:33:40 +0200 From: Mario Kleiner User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Daniel Vetter Subject: Re: Intel-kms in Linux-4.2rc causes regression due to dithering always on. References: <55C3D803.5070904@gmail.com> <55C3E3A0.8040503@gmail.com> <20150807071430.GG17734@phenom.ffwll.local> In-Reply-To: <20150807071430.GG17734@phenom.ffwll.local> Cc: intel-gfx , "dri-devel@lists.freedesktop.org" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 08/07/2015 09:14 AM, Daniel Vetter wrote: > On Fri, Aug 07, 2015 at 12:45:52AM +0200, Mario Kleiner wrote: >> On 08/07/2015 12:12 AM, Daniel Vetter wrote: >>> On Thu, Aug 6, 2015 at 11:56 PM, Mario Kleiner >>> wrote: >>>> Hi Daniel and all, >>>> >>>> since Linux 4.2 (tested with rc4), i think this commit >>>> d328c9d78d64ca11e744fe227096990430a88477 >>>> "drm/i915: Select starting pipe bpp irrespective or the primary plane" >>>> >>>> causes trouble for me and my users, as tested on Intel HD Ironlake and Ivy >>>> Bridge with MiniDP->Singlelink-DVI adapter -> Measurement device. >>>> >>>> Afaics it causes dithering to always be enabled on a regular 8bpc >>>> framebuffer, even when outputting to a 8 bpc DVI-D output, and that >>>> dithering causes my display measurement equipment and other special display >>>> devices used for neuro-science and medical applications to fail. This >>>> equipment requires an identity passthrough of 8 bpc framebuffer pixels to >>>> the digital outputs, iow. dithering off. >>>> >>>> Log output on Linux 4.1 (good): >>>> >>>> Aug 1 06:39:26 twisty kernel: [ 154.175394] >>>> [drm:connected_sink_compute_bpp] [CONNECTOR:35:HDMI-A-1] checking for sink >>>> bpp constrains >>>> Aug 1 06:39:26 twisty kernel: [ 154.175396] >>>> [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output >>>> Aug 1 06:39:26 twisty kernel: [ 154.175397] >>>> [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI >>>> Aug 1 06:39:26 twisty kernel: [ 154.175400] [drm:ironlake_check_fdi_lanes] >>>> checking fdi config on pipe A, lanes 1 >>>> Aug 1 06:39:26 twisty kernel: [ 154.175402] >>>> [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 >>>> Aug 1 06:39:26 twisty kernel: [ 154.175403] [drm:intel_dump_pipe_config] >>>> [CRTC:20][modeset] config for pipe A >>>> Aug 1 06:39:26 twisty kernel: [ 154.175404] [drm:intel_dump_pipe_config] >>>> cpu_transcoder: A >>>> Aug 1 06:39:26 twisty kernel: [ 154.175405] [drm:intel_dump_pipe_config] >>>> pipe bpp: 24, dithering: 0 >>>> >>>> Log output on Linux 4.2-rc4 (bad): >>>> >>>> Aug 1 06:21:31 twisty kernel: [ 200.924831] >>>> [drm:connected_sink_compute_bpp] [CONNECTOR:36:HDMI-A-1] checking for sink >>>> bpp constrains >>>> Aug 1 06:21:31 twisty kernel: [ 200.924832] >>>> [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default >>>> limit of 24 >>>> Aug 1 06:21:31 twisty kernel: [ 200.924834] >>>> [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output >>>> Aug 1 06:21:31 twisty kernel: [ 200.924835] >>>> [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI >>>> Aug 1 06:21:31 twisty kernel: [ 200.924838] [drm:ironlake_check_fdi_lanes] >>>> checking fdi config on pipe A, lanes 1 >>>> Aug 1 06:21:31 twisty kernel: [ 200.924840] >>>> [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 24, dithering: 1 >>>> Aug 1 06:21:31 twisty kernel: [ 200.924841] [drm:intel_dump_pipe_config] >>>> [CRTC:21][modeset] config ffff880131a5c800 for pipe A >>>> Aug 1 06:21:31 twisty kernel: [ 200.924842] [drm:intel_dump_pipe_config] >>>> cpu_transcoder: A >>>> Aug 1 06:21:31 twisty kernel: [ 200.924843] [drm:intel_dump_pipe_config] >>>> pipe bpp: 24, dithering: 1 >>>> >>>> Ideas what to do about this? >>> >>> Well I somehow assumed the dither bit would be sane and not wreak >>> havoc with the lower bits when they would fit into the final bpc pipe >>> mode ... Can you confirm with your equipment that we seem to be doing >>> 8bpc->6bpc dithering on the 8bpc sink? >>> >> >> It will need a bit of work to find this out when i'm back in the lab. So far >> i just know something bad is happening to the signal and i assume it's the >> dithering, because the visual error pattern of messiness looks like that >> caused by dithering. E.g., on a static framebuffer i see some repeating >> pattern over the screen, but the pattern changes with every OpenGL >> bufferswap, even if i swap to the same fb content, as if the swap triggers >> some change of the spatial dither pattern (assuming PIPECONF_DITHER_TYPE_SP >> = spatial dithering?) >> >>> If that's the case we simply limit to only ever dither when the sink >>> is 6bpc, and not in any other case. >>> -Daniel >>> >> >> That would be an improvement for my immediate problem if that works. But >> assuming we have 10 bpc framebuffers at some point, dithering 10 bpc -> 8 >> bpc would also have some practical use. >> >> Probably some dynamic check would be good, a la if there is a mismatch >> between the max(bpc) over all active planes and the supported depth of the >> sink then dither? >> >> It's not clear to me where the dithering happens on intel hw. I'd expected >> that with a 24 bpp framebuffer feeding into a 24 bpp pipe, dithering simply >> wouldn't do anything even if enabled. > > Yeah my assumption was that if you run the pipe at a given bpc it will > just pass through anything that fits and only dither the additional bits. > But obviously that's not how the hardware works ... > > The problem with adaptive schemes is that we have multiple planes nowadays > and they might all run at different depths. And dither seems to be > happening at the pipe/overall level (at least there's only one bit). Of > course this wouldn't be a problem if the thing wouldn't mangle bits which > should pass! > > Anyway if we can confirm this I think dithering for only 6bpc should be > ok. > -Daniel > Ok, did some testing and the results are weird. The procedure was to render a fullscreen constant color image via OpenGL - set constant color framebuffer via glClearColor + glClear + bufferswap, using pageflips through unredirected fullscreen windows. Gamma tables were set to identity mapping. I stepped through all 256 R = G = B = Ref. values and my equipment captured the actual single-link DVI-D video input signal of the topmost scanline. The table below shows the actual value in the framebuffer vs. the readback 8 bpc values of the red channel for the first 10 pixels in the scanline, green and blue channels have same result: >> >> On Linux 4.2-rc5, Intel HD Ironlake, 24 bpp fb,pipeconf etc. via DVI-D. Ref 0: 0 0 0 0 0 0 0 0 0 0 Ref 1: 1 0 1 0 1 0 1 0 1 0 Ref 2: 2 1 2 1 2 1 2 1 2 1 Ref 3: 3 2 3 2 3 2 3 2 3 2 Ref 4: 4 3 4 3 4 3 4 3 4 3 Ref 5: 5 4 5 4 5 4 5 4 5 4 Ref 6: 6 5 6 5 6 5 6 5 6 5 Ref 7: 7 6 7 6 7 6 7 6 7 6 Ref 8: 8 7 8 7 8 7 8 7 8 7 Ref 9: 9 8 9 8 9 8 9 8 9 8 Ref 10: 10 9 10 9 10 9 10 9 10 9 Ref 11: 11 10 11 10 11 10 11 10 11 10 Ref 12: 12 11 12 11 12 11 12 11 12 11 Ref 13: 13 12 13 12 13 12 13 12 13 12 Ref 14: 14 13 14 13 14 13 14 13 14 13 Ref 15: 15 14 15 14 15 14 15 14 15 14 Ref 16: 16 15 16 15 16 15 16 15 16 15 Ref 17: 17 16 17 16 17 16 17 16 17 16 Ref 18: 18 17 18 17 18 17 18 17 18 17 Ref 19: 19 18 19 18 19 18 19 18 19 18 Ref 20: 20 19 20 19 20 19 20 19 20 19 Ref 21: 21 20 21 20 21 20 21 20 21 20 Ref 22: 22 21 22 21 22 21 22 21 22 21 Ref 23: 23 22 23 22 23 22 23 22 23 22 Ref 24: 24 23 24 23 24 23 24 23 24 23 Ref 25: 25 24 25 24 25 24 25 24 25 24 Ref 26: 26 25 26 25 26 25 26 25 26 25 Ref 27: 27 26 27 26 27 26 27 26 27 26 Ref 28: 28 27 28 27 28 27 28 27 28 27 Ref 29: 29 28 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Ref 229: 229 229 229 229 229 229 229 229 229 229 Ref 230: 230 230 230 230 230 230 230 230 230 230 Ref 231: 231 231 231 231 231 231 231 231 231 231 Ref 232: 232 232 232 232 232 232 232 232 232 232 Ref 233: 233 233 233 233 233 233 233 233 233 233 Ref 234: 234 234 234 234 234 234 234 234 234 234 Ref 235: 235 235 235 235 235 235 235 235 235 235 Ref 236: 236 236 236 236 236 236 236 236 236 236 Ref 237: 237 237 237 237 237 237 237 237 237 237 Ref 238: 238 238 238 238 238 238 238 238 238 238 Ref 239: 239 239 239 239 239 239 239 239 239 239 Ref 240: 240 240 240 240 240 240 240 240 240 240 Ref 241: 241 241 241 241 241 241 241 241 241 241 Ref 242: 242 242 242 242 242 242 242 242 242 242 Ref 243: 243 243 243 243 243 243 243 243 243 243 Ref 244: 244 244 244 244 244 244 244 244 244 244 Ref 245: 245 245 245 245 245 245 245 245 245 245 Ref 246: 246 246 246 246 246 246 246 246 246 246 Ref 247: 247 247 247 247 247 247 247 247 247 247 Ref 248: 248 248 248 248 248 248 248 248 248 248 Ref 249: 249 249 249 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So it's not dithering the 8 bpc fb on the 8 bpc pipe to 6 bpc output, as all 256 values are in the output, but it is somehow screwing with the 8 bpc signal for no reason. Values >= 192 are unaffected, values between 0 and 127 get treated slightly different wrong than between 128 and 191. On Linux <= 4.1 the output is as expected. If i apply this patch to force dithering off, then the problem is fixed on 4.2-rc: if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) val |= PIPECONF_INTERLACED_ILK; So the weirdness is triggered by dither enable on a 24 bpp fb feeding into the 24 bpp pipe, at least on the ironlake code path. Don't have a haswell part atm. to test that. -mario --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8622,8 +8622,10 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc) BUG(); } - if (intel_crtc->config->dither) - val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); + if (intel_crtc->config->dither) { + DRM_INFO("Ironlake wants dithering, but skipping dither enable!\n"); + /* val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); */ + }