From patchwork Wed Aug 19 11:46:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 11723637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E886B618 for ; Wed, 19 Aug 2020 11:47:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C74B3207BB for ; Wed, 19 Aug 2020 11:47:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="XPoNKr4U" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C74B3207BB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EC1B26E264; Wed, 19 Aug 2020 11:47:06 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id AF6796E223 for ; Wed, 19 Aug 2020 11:46:24 +0000 (UTC) Received: from mail.kernel.org (ip5f5ad5a3.dynamic.kabel-deutschland.de [95.90.213.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 04C6A22D6D; Wed, 19 Aug 2020 11:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597837584; bh=0s3pmtILVSiuI77kiYarCgl3FUbdNZSJJENxk4HNs1c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XPoNKr4UNTqnAzpnnXX0ra1UVzx27ph7DOeQ7Lxg7GLPBzAJk+TZgZwglUIovjO2C Ox4rol4IoNMRrIBPrZttvUxhNAQeUcTpgYcArKxrbQqhv+FTLNfCzOp3uPn61YI22K D9se5drVv7bB9w8L2f0tMtFoW2knYrdC4sR1YRZo= Received: from mchehab by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1k8MXt-00EucG-PZ; Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Subject: [PATCH 49/49] dt: display: Add binds for the DPE and DSI controller for Kirin 960/970 Date: Wed, 19 Aug 2020 13:46:17 +0200 Message-Id: <6471642f74779fecfc9d5e990d90f9475d8b32d4.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jesper Dangaard Brouer , Daniel Borkmann , Manivannan Sadhasivam , Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, John Fastabend , linuxarm@huawei.com, dri-devel , Alexei Starovoitov , David Airlie , Rob Herring , Wei Xu , netdev@vger.kernel.org, mauro.chehab@huawei.com, Jakub Kicinski , bpf@vger.kernel.org, "David S. Miller" , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a description of the bindings used by Kirin 960/970 Display Serial Interface (DSI) controller and by its Display Engine (DPE). Signed-off-by: Mauro Carvalho Chehab --- .../display/hisilicon,hi3660-dpe.yaml | 99 +++++++++++++++++ .../display/hisilicon,hi3660-dsi.yaml | 102 ++++++++++++++++++ .../boot/dts/hisilicon/hikey970-drm.dtsi | 4 +- 3 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml create mode 100644 Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml diff --git a/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml new file mode 100644 index 000000000000..074997354417 --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/hisilicon,hi3660-dpe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon SPMI controller + +maintainers: + - Mauro Carvalho Chehab + +description: | + The HiSilicon Display Engine (DPE) s the display controller which grab + image data from memory, do composition, do post image processing, + generate RGB timing stream and transfer to DSI. + +properties: + $nodename: + pattern: "dpe@[0-9a-f]+" + + compatible: + enum: + - hisilicon,kirin960-dpe + - hisilicon,kirin970-dpe + + reg: + minItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + description: Clocks used by the ISP and by the display + + clock-names: + description: Names for the clock lines + + dma-coherent: true + + port: + type: object + description: A port node pointing to the display output endpoint. + + + iommu-info: + type: object + description: IOMMU address and size to be used by GPU + + properties: + start-addr: + const: start address for IOMMU + size: + const: size of the mapped region + +examples: + - | + dpe: dpe@e8600000 { + compatible = "hisilicon,kirin970-dpe"; + memory-region = <&drm_dma_reserved>; + reg = <0 0xE8600000 0 0xC0000>, + <0 0xFFF35000 0 0x1000>, + <0 0xFFF0A000 0 0x1000>, + <0 0xE8A09000 0 0x1000>, + <0 0xE86C0000 0 0x10000>, + <0 0xFFF31000 0 0x1000>, + <0 0xE87FF000 0 0x1000>; + + interrupts = <0 245 4>; + + clocks = <&media1_crg HI3670_ACLK_GATE_DSS>, + <&media1_crg HI3670_PCLK_GATE_DSS>, + <&media1_crg HI3670_CLK_GATE_EDC0>, + <&media1_crg HI3670_CLK_GATE_LDI0>, + <&media1_crg HI3670_CLK_GATE_DSS_AXI_MM>, + <&media1_crg HI3670_PCLK_GATE_MMBUF>, + <&crg_ctrl HI3670_PCLK_GATE_PCTRL>; + + clock-names = "aclk_dss", + "pclk_dss", + "clk_edc0", + "clk_ldi0", + "clk_dss_axi_mm", + "pclk_mmbuf", + "pclk_pctrl"; + + dma-coherent; + + port { + dpe_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + + iommu_info { + start-addr = <0x8000>; + size = <0xbfff8000>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml new file mode 100644 index 000000000000..2265267fc53d --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/hisilicon,hi3660-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon SPMI controller + +maintainers: + - Mauro Carvalho Chehab + +description: | + The HiSilicon Display Serial Interface (DSI) Host Controller for + Kirin 960 and 970 resides in the middle of display controller and + an external HDMI converter or panel. + +properties: + $nodename: + pattern: "dsi@[0-9a-f]+" + + compatible: + enum: + - hisilicon,kirin960-dsi + - hisilicon,kirin970-dsi + + reg: + minItems: 1 + maxItems: 4 + + clocks: + minItems: 1 + maxItems: 8 + description: Clocks used by the ISP and by the display. + + clock-names: + description: Names for the clock lines. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + mux-gpio: + description: GPIO used by the mux. + + ports: + type: object + description: Display input and output ports. + +examples: + - | + dsi: dsi@e8601000 { + compatible = "hisilicon,kirin970-dsi"; + reg = <0 0xE8601000 0 0x7F000>, + <0 0xFFF35000 0 0x1000>, + <0 0xE8A09000 0 0x1000>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_TXDPHY0_REF>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY1_REF>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY0_CFG>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY1_CFG>, + <&crg_ctrl HI3670_PCLK_GATE_DSI0>, + <&crg_ctrl HI3670_PCLK_GATE_DSI1>; + clock-names = "clk_txdphy0_ref", + "clk_txdphy1_ref", + "clk_txdphy0_cfg", + "clk_txdphy1_cfg", + "pclk_dsi0", + "pclk_dsi1"; + + #address-cells = <1>; + #size-cells = <0>; + mux-gpio = <&gpio25 7 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dpe_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dsi_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7533_in>; + }; + + dsi_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&panel0_in>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi index 503c7c9425c8..5758d7d181e5 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 / { - dpe: dpe@E8600000 { + dpe: dpe@e8600000 { compatible = "hisilicon,kirin970-dpe"; memory-region = <&drm_dma_reserved>; // DSS, PERI_CRG, SCTRL, PCTRL, NOC_DSS_Service_Target, PMCTRL, MEDIA_CRG @@ -44,7 +44,7 @@ iommu_info { }; }; - dsi: dsi@E8601000 { + dsi: dsi@e8601000 { compatible = "hisilicon,kirin970-dsi"; reg = <0 0xE8601000 0 0x7F000>, <0 0xFFF35000 0 0x1000>,