From patchwork Mon Dec 4 18:37:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 10092499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D0BC36035E for ; Tue, 5 Dec 2017 08:50:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0EE829500 for ; Tue, 5 Dec 2017 08:50:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B4A7529511; Tue, 5 Dec 2017 08:50:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 60CB529500 for ; Tue, 5 Dec 2017 08:50:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3D276E43D; Tue, 5 Dec 2017 08:49:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7322F6E058 for ; Mon, 4 Dec 2017 18:38:43 +0000 (UTC) Received: from submarine.cbg.collabora.co.uk (unknown [IPv6:2a00:5f00:102:0:d0a5:4565:9830:3aaf]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: gtucker) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 42A442702E1; Mon, 4 Dec 2017 18:38:42 +0000 (GMT) From: Guillaume Tucker To: Jonathan Hunter , David Airlie Subject: [PATCH 2/2] drm/tegra: sor: Fix hang on tegra124 due to NULL clk_out Date: Mon, 4 Dec 2017 18:37:59 +0000 Message-Id: <79b4a60f1d624b16eaef06258318861d4407fecd.1512411775.git.guillaume.tucker@collabora.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-Mailman-Approved-At: Tue, 05 Dec 2017 08:49:51 +0000 Cc: Guillaume Tucker , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, Thierry Reding , linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP When neither HDMI nor DP is supported such as on the tegra124, the sor->clk_out is not initialised and remains NULL. In this case, the parent clock can't be assigned to it so revert to the previous behaviour of assigning it to the main sor->clock instead. This fixes a kernel hang on tegra124. Fixes: e1335e2f0cfc ("drm/tegra: sor: Reimplement pad clock") Signed-off-by: Guillaume Tucker CC: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index b0a1dedac802..8d2e29c9ab2b 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -255,7 +255,7 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) clk_disable_unprepare(sor->clk); - err = clk_set_parent(sor->clk_out, parent); + err = clk_set_parent(sor->clk_out ? sor->clk_out : sor->clk, parent); if (err < 0) return err; @@ -2698,15 +2698,19 @@ static int tegra_sor_probe(struct platform_device *pdev) sor->clk_pad = NULL; } - /* - * The bootloader may have set up the SOR such that it's module clock - * is sourced by one of the display PLLs. However, that doesn't work - * without properly having set up other bits of the SOR. - */ - err = clk_set_parent(sor->clk_out, sor->clk_safe); - if (err < 0) { - dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); - goto remove; + if (sor->clk_out) { + /* + * The bootloader may have set up the SOR such that its module + * clock is sourced by one of the display PLLs. However, that + * doesn't work without properly having set up other bits of + * the SOR. + */ + err = clk_set_parent(sor->clk_out, sor->clk_safe); + if (err < 0) { + dev_err(&pdev->dev, "failed to use safe clock: %d\n", + err); + goto remove; + } } platform_set_drvdata(pdev, sor);