diff mbox

[02/11] radeon: evergreen: Fix probable mask then right shift defects

Message ID 88c64cce88264069e0e1637fc874e699e5b226f6.1414387334.git.joe@perches.com (mailing list archive)
State New, archived
Headers show

Commit Message

Joe Perches Oct. 27, 2014, 5:24 a.m. UTC
Precedence of & and >> is not the same and is not left to right.
shift has higher precedence and should be done after the mask.

Add parentheses around the mask.

Use the already #defined values instead of hardcoding.

Signed-off-by: Joe Perches <joe@perches.com>
---
 drivers/gpu/drm/radeon/evergreen.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Michel Dänzer Oct. 27, 2014, 9:14 a.m. UTC | #1
On 27.10.2014 14:24, Joe Perches wrote:
> Precedence of & and >> is not the same and is not left to right.
> shift has higher precedence and should be done after the mask.
>
> Add parentheses around the mask.
>
> Use the already #defined values instead of hardcoding.
>
> Signed-off-by: Joe Perches <joe@perches.com>
> ---
>   drivers/gpu/drm/radeon/evergreen.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
> index a31f1ca..a97a685 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -3303,7 +3303,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
>   	rdev->config.evergreen.tile_config |=
>   		((gb_addr_config & 0x30000000) >> 28) << 12;
>
> -	num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
> +	num_shader_engines = ((gb_addr_config & NUM_SHADER_ENGINES_MASK)
> +			      >> NUM_SHADER_ENGINES) + 1;
                                  ^^^^^^^^^^^^^^^^^^
I think this should be NUM_SHADER_ENGINES_SHIFT?

Looks good to me other than that.
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index a31f1ca..a97a685 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3303,7 +3303,8 @@  static void evergreen_gpu_init(struct radeon_device *rdev)
 	rdev->config.evergreen.tile_config |=
 		((gb_addr_config & 0x30000000) >> 28) << 12;
 
-	num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
+	num_shader_engines = ((gb_addr_config & NUM_SHADER_ENGINES_MASK)
+			      >> NUM_SHADER_ENGINES) + 1;
 
 	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
 		u32 efuse_straps_4;