From patchwork Tue Mar 21 15:06:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 9636757 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 872CB602CC for ; Tue, 21 Mar 2017 15:07:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 788D02018E for ; Tue, 21 Mar 2017 15:07:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6BE372793B; Tue, 21 Mar 2017 15:07:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CCB672018E for ; Tue, 21 Mar 2017 15:07:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61D696E716; Tue, 21 Mar 2017 15:07:21 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id ECCCE6E711 for ; Tue, 21 Mar 2017 15:07:18 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2LF6thi015043; Tue, 21 Mar 2017 10:06:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1490108815; bh=nv2FFJA0O0dxb86cKgtubx8vrx72MQuKtZsiqn4INxw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=veMeNksBvgl7yifuw0pf8FR31M6ymWafHuKvx0mwMOEerh7IsBGerykSeNKpNDn8b 3b2h8jNRXX+EO7IBuhCY8YkVgMxMUveAfKB9VekW31+0KnVcsqOyBriUC69WTG7lru kQG4kBld1b25UIPq3/1QGhFQ9zBFaWzcdsClWq3k= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2LF6nu0029145; Tue, 21 Mar 2017 10:06:49 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Tue, 21 Mar 2017 10:06:48 -0500 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2LF6j1p010986; Tue, 21 Mar 2017 10:06:48 -0500 From: Jyri Sarha To: Subject: [PATCH v3 2/5] drm/omap: Rename enum omap_plane to enum omap_plane_id Date: Tue, 21 Mar 2017 17:06:39 +0200 Message-ID: <89f9c579385fff14558d1104290064696aa3ddeb.1490108707.git.jsarha@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 Cc: tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, Jyri Sarha X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The enum omap_plane conflicted with the same struct name for omapdrm plane private data. This rename should solve the conflict. The rename was implement with this very simple coccinelle patch: ------------------------ @@ @@ enum -omap_plane +omap_plane_id ------------------------ The patch was applied like this: spatch --sp-file --all-includes --in-place --dir drivers/gpu/drm/omapdrm The above patch did not rename the actual enum definition. That was added manually on top of the spatch changes. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/dss/dispc.c | 122 ++++++++++++++++------------- drivers/gpu/drm/omapdrm/dss/dispc.h | 62 +++++++-------- drivers/gpu/drm/omapdrm/dss/dss.h | 5 +- drivers/gpu/drm/omapdrm/dss/dss_features.c | 6 +- drivers/gpu/drm/omapdrm/dss/dss_features.h | 4 +- drivers/gpu/drm/omapdrm/dss/omapdss.h | 15 ++-- 6 files changed, 114 insertions(+), 100 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index d956e626..17712a3 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -303,8 +303,8 @@ struct color_conv_coef { static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); -static unsigned long dispc_plane_pclk_rate(enum omap_plane plane); -static unsigned long dispc_plane_lclk_rate(enum omap_plane plane); +static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane); +static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane); static inline void dispc_write_reg(const u16 idx, u32 val) { @@ -657,7 +657,7 @@ bool dispc_wb_go_busy(void) void dispc_wb_go(void) { - enum omap_plane plane = OMAP_DSS_WB; + enum omap_plane_id plane = OMAP_DSS_WB; bool enable, go; enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; @@ -674,29 +674,33 @@ void dispc_wb_go(void) REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); } -static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) +static void dispc_ovl_write_firh_reg(enum omap_plane_id plane, int reg, + u32 value) { dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); } -static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) +static void dispc_ovl_write_firhv_reg(enum omap_plane_id plane, int reg, + u32 value) { dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); } -static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) +static void dispc_ovl_write_firv_reg(enum omap_plane_id plane, int reg, + u32 value) { dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); } -static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) +static void dispc_ovl_write_firh2_reg(enum omap_plane_id plane, int reg, + u32 value) { BUG_ON(plane == OMAP_DSS_GFX); dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); } -static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, +static void dispc_ovl_write_firhv2_reg(enum omap_plane_id plane, int reg, u32 value) { BUG_ON(plane == OMAP_DSS_GFX); @@ -704,14 +708,15 @@ static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); } -static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) +static void dispc_ovl_write_firv2_reg(enum omap_plane_id plane, int reg, + u32 value) { BUG_ON(plane == OMAP_DSS_GFX); dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); } -static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, +static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc, int fir_vinc, int five_taps, enum omap_color_component color_comp) { @@ -757,7 +762,7 @@ static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, } -static void dispc_ovl_write_color_conv_coef(enum omap_plane plane, +static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane, const struct color_conv_coef *ct) { #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) @@ -793,27 +798,27 @@ static void dispc_setup_color_conv_coef(void) dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); } -static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) +static void dispc_ovl_set_ba0(enum omap_plane_id plane, u32 paddr) { dispc_write_reg(DISPC_OVL_BA0(plane), paddr); } -static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) +static void dispc_ovl_set_ba1(enum omap_plane_id plane, u32 paddr) { dispc_write_reg(DISPC_OVL_BA1(plane), paddr); } -static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) +static void dispc_ovl_set_ba0_uv(enum omap_plane_id plane, u32 paddr) { dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); } -static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) +static void dispc_ovl_set_ba1_uv(enum omap_plane_id plane, u32 paddr) { dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); } -static void dispc_ovl_set_pos(enum omap_plane plane, +static void dispc_ovl_set_pos(enum omap_plane_id plane, enum omap_overlay_caps caps, int x, int y) { u32 val; @@ -826,7 +831,7 @@ static void dispc_ovl_set_pos(enum omap_plane plane, dispc_write_reg(DISPC_OVL_POSITION(plane), val); } -static void dispc_ovl_set_input_size(enum omap_plane plane, int width, +static void dispc_ovl_set_input_size(enum omap_plane_id plane, int width, int height) { u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); @@ -837,7 +842,7 @@ static void dispc_ovl_set_input_size(enum omap_plane plane, int width, dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); } -static void dispc_ovl_set_output_size(enum omap_plane plane, int width, +static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width, int height) { u32 val; @@ -852,7 +857,7 @@ static void dispc_ovl_set_output_size(enum omap_plane plane, int width, dispc_write_reg(DISPC_OVL_SIZE(plane), val); } -static void dispc_ovl_set_zorder(enum omap_plane plane, +static void dispc_ovl_set_zorder(enum omap_plane_id plane, enum omap_overlay_caps caps, u8 zorder) { if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) @@ -872,7 +877,7 @@ static void dispc_ovl_enable_zorder_planes(void) REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); } -static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, +static void dispc_ovl_set_pre_mult_alpha(enum omap_plane_id plane, enum omap_overlay_caps caps, bool enable) { if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) @@ -881,7 +886,7 @@ static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); } -static void dispc_ovl_setup_global_alpha(enum omap_plane plane, +static void dispc_ovl_setup_global_alpha(enum omap_plane_id plane, enum omap_overlay_caps caps, u8 global_alpha) { static const unsigned shifts[] = { 0, 8, 16, 24, }; @@ -894,17 +899,17 @@ static void dispc_ovl_setup_global_alpha(enum omap_plane plane, REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); } -static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) +static void dispc_ovl_set_pix_inc(enum omap_plane_id plane, s32 inc) { dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); } -static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) +static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc) { dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); } -static void dispc_ovl_set_color_mode(enum omap_plane plane, +static void dispc_ovl_set_color_mode(enum omap_plane_id plane, enum omap_color_mode color_mode) { u32 m = 0; @@ -985,7 +990,7 @@ static void dispc_ovl_set_color_mode(enum omap_plane plane, REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); } -static void dispc_ovl_configure_burst_type(enum omap_plane plane, +static void dispc_ovl_configure_burst_type(enum omap_plane_id plane, enum omap_dss_rotation_type rotation_type) { if (dss_has_feature(FEAT_BURST_2D) == 0) @@ -997,7 +1002,8 @@ static void dispc_ovl_configure_burst_type(enum omap_plane plane, REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); } -void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) +void dispc_ovl_set_channel_out(enum omap_plane_id plane, + enum omap_channel channel) { int shift; u32 val; @@ -1059,7 +1065,7 @@ void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) } EXPORT_SYMBOL(dispc_ovl_set_channel_out); -static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) +static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane) { int shift; u32 val; @@ -1101,12 +1107,12 @@ static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) void dispc_wb_set_channel_in(enum dss_writeback_channel channel) { - enum omap_plane plane = OMAP_DSS_WB; + enum omap_plane_id plane = OMAP_DSS_WB; REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16); } -static void dispc_ovl_set_burst_size(enum omap_plane plane, +static void dispc_ovl_set_burst_size(enum omap_plane_id plane, enum omap_burst_size burst_size) { static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; @@ -1128,7 +1134,7 @@ static void dispc_configure_burst_sizes(void) dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); } -static u32 dispc_ovl_get_burst_size(enum omap_plane plane) +static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane) { unsigned unit = dss_feat_get_burst_size_unit(); /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ @@ -1163,7 +1169,8 @@ static void dispc_mgr_set_cpr_coef(enum omap_channel channel, dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); } -static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) +static void dispc_ovl_set_vid_color_conv(enum omap_plane_id plane, + bool enable) { u32 val; @@ -1174,7 +1181,7 @@ static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); } -static void dispc_ovl_enable_replication(enum omap_plane plane, +static void dispc_ovl_enable_replication(enum omap_plane_id plane, enum omap_overlay_caps caps, bool enable) { static const unsigned shifts[] = { 5, 10, 10, 10 }; @@ -1271,7 +1278,7 @@ static void dispc_init_fifos(void) } } -static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) +static u32 dispc_ovl_get_fifo_size(enum omap_plane_id plane) { int fifo; u32 size = 0; @@ -1284,7 +1291,8 @@ static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) return size; } -void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) +void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, + u32 high) { u8 hi_start, hi_end, lo_start, lo_end; u32 unit; @@ -1333,7 +1341,7 @@ void dispc_enable_fifomerge(bool enable) REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); } -void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, +void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, bool manual_update) { @@ -1380,7 +1388,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, } } -static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable) +static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable) { int bit; @@ -1392,7 +1400,7 @@ static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable) REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); } -static void dispc_ovl_set_mflag_threshold(enum omap_plane plane, +static void dispc_ovl_set_mflag_threshold(enum omap_plane_id plane, int low, int high) { dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), @@ -1456,7 +1464,7 @@ static void dispc_init_mflag(void) } } -static void dispc_ovl_set_fir(enum omap_plane plane, +static void dispc_ovl_set_fir(enum omap_plane_id plane, int hinc, int vinc, enum omap_color_component color_comp) { @@ -1479,7 +1487,8 @@ static void dispc_ovl_set_fir(enum omap_plane plane, } } -static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) +static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu, + int vaccu) { u32 val; u8 hor_start, hor_end, vert_start, vert_end; @@ -1493,7 +1502,8 @@ static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) dispc_write_reg(DISPC_OVL_ACCU0(plane), val); } -static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) +static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu, + int vaccu) { u32 val; u8 hor_start, hor_end, vert_start, vert_end; @@ -1507,7 +1517,7 @@ static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) dispc_write_reg(DISPC_OVL_ACCU1(plane), val); } -static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, +static void dispc_ovl_set_vid_accu2_0(enum omap_plane_id plane, int haccu, int vaccu) { u32 val; @@ -1516,7 +1526,7 @@ static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); } -static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, +static void dispc_ovl_set_vid_accu2_1(enum omap_plane_id plane, int haccu, int vaccu) { u32 val; @@ -1525,7 +1535,7 @@ static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); } -static void dispc_ovl_set_scale_param(enum omap_plane plane, +static void dispc_ovl_set_scale_param(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, bool five_taps, u8 rotation, @@ -1541,7 +1551,7 @@ static void dispc_ovl_set_scale_param(enum omap_plane plane, dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); } -static void dispc_ovl_set_accu_uv(enum omap_plane plane, +static void dispc_ovl_set_accu_uv(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, bool ilace, enum omap_color_mode color_mode, u8 rotation) { @@ -1629,7 +1639,7 @@ static void dispc_ovl_set_accu_uv(enum omap_plane plane, dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); } -static void dispc_ovl_set_scaling_common(enum omap_plane plane, +static void dispc_ovl_set_scaling_common(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, bool ilace, bool five_taps, @@ -1683,7 +1693,7 @@ static void dispc_ovl_set_scaling_common(enum omap_plane plane, dispc_ovl_set_vid_accu1(plane, 0, accu1); } -static void dispc_ovl_set_scaling_uv(enum omap_plane plane, +static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, bool ilace, bool five_taps, @@ -1763,7 +1773,7 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane plane, REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); } -static void dispc_ovl_set_scaling(enum omap_plane plane, +static void dispc_ovl_set_scaling(enum omap_plane_id plane, u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, bool ilace, bool five_taps, @@ -1787,7 +1797,8 @@ static void dispc_ovl_set_scaling(enum omap_plane plane, rotation); } -static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, +static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, + u8 rotation, enum omap_dss_rotation_type rotation_type, bool mirroring, enum omap_color_mode color_mode) { @@ -2619,7 +2630,7 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, return 0; } -static int dispc_ovl_setup_common(enum omap_plane plane, +static int dispc_ovl_setup_common(enum omap_plane_id plane, enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, u16 out_width, u16 out_height, enum omap_color_mode color_mode, @@ -2817,7 +2828,8 @@ static int dispc_ovl_setup_common(enum omap_plane plane, return 0; } -int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, +int dispc_ovl_setup(enum omap_plane_id plane, + const struct omap_overlay_info *oi, bool replication, const struct videomode *vm, bool mem_to_mem) { @@ -2848,7 +2860,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi, { int r; u32 l; - enum omap_plane plane = OMAP_DSS_WB; + enum omap_plane_id plane = OMAP_DSS_WB; const int pos_x = 0, pos_y = 0; const u8 zorder = 0, global_alpha = 0; const bool replication = false; @@ -2911,7 +2923,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi, return r; } -int dispc_ovl_enable(enum omap_plane plane, bool enable) +int dispc_ovl_enable(enum omap_plane_id plane, bool enable) { DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); @@ -2921,7 +2933,7 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable) } EXPORT_SYMBOL(dispc_ovl_enable); -bool dispc_ovl_enabled(enum omap_plane plane) +bool dispc_ovl_enabled(enum omap_plane_id plane) { return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); } @@ -3389,7 +3401,7 @@ static unsigned long dispc_core_clk_rate(void) return dispc.core_clk_rate; } -static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) +static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane) { enum omap_channel channel; @@ -3401,7 +3413,7 @@ static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) return dispc_mgr_pclk_rate(channel); } -static unsigned long dispc_plane_lclk_rate(enum omap_plane plane) +static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane) { enum omap_channel channel; diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.h b/drivers/gpu/drm/omapdrm/dss/dispc.h index bc1d812..003adce 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.h +++ b/drivers/gpu/drm/omapdrm/dss/dispc.h @@ -353,7 +353,7 @@ static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel) } /* DISPC overlay register base addresses */ -static inline u16 DISPC_OVL_BASE(enum omap_plane plane) +static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -373,7 +373,7 @@ static inline u16 DISPC_OVL_BASE(enum omap_plane plane) } /* DISPC overlay register offsets */ -static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane) +static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -389,7 +389,7 @@ static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane) +static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -405,7 +405,7 @@ static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane) +static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -425,7 +425,7 @@ static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane) +static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -445,7 +445,7 @@ static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_POS_OFFSET(enum omap_plane plane) +static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -460,7 +460,7 @@ static inline u16 DISPC_POS_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane) +static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -476,7 +476,7 @@ static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane) +static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -493,7 +493,7 @@ static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane) +static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -513,7 +513,7 @@ static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane) +static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -530,7 +530,7 @@ static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane) +static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -547,7 +547,7 @@ static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane) +static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -564,7 +564,7 @@ static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane) +static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -581,7 +581,7 @@ static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane) +static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -597,7 +597,7 @@ static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane) +static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -613,7 +613,7 @@ static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane) +static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -631,7 +631,7 @@ static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane) +static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -651,7 +651,7 @@ static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane) +static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -670,7 +670,7 @@ static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane) } -static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane) +static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -688,7 +688,7 @@ static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane) +static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -708,7 +708,7 @@ static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane) +static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -726,7 +726,7 @@ static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane) +static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -747,7 +747,7 @@ static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane) } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i) +static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i) { switch (plane) { case OMAP_DSS_GFX: @@ -766,7 +766,7 @@ static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i) } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i) +static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i) { switch (plane) { case OMAP_DSS_GFX: @@ -787,7 +787,7 @@ static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i) } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i) +static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i) { switch (plane) { case OMAP_DSS_GFX: @@ -806,7 +806,7 @@ static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i) } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i) +static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i) { switch (plane) { case OMAP_DSS_GFX: @@ -827,7 +827,7 @@ static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i) } /* coef index i = {0, 1, 2, 3, 4,} */ -static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i) +static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i) { switch (plane) { case OMAP_DSS_GFX: @@ -845,7 +845,7 @@ static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i) } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i) +static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i) { switch (plane) { case OMAP_DSS_GFX: @@ -865,7 +865,7 @@ static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i) } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i) +static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i) { switch (plane) { case OMAP_DSS_GFX: @@ -885,7 +885,7 @@ static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i) } } -static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane) +static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: @@ -902,7 +902,7 @@ static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane) } } -static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane) +static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane) { switch (plane) { case OMAP_DSS_GFX: diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index 78f6fc7..9b769dc 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -368,8 +368,9 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, struct dispc_clock_info *cinfo); -void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high); -void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, +void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, + u32 high); +void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, bool manual_update); diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index ee5b93c..8ac3cbc 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -802,18 +802,18 @@ enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel return omap_current_dss_features->supported_outputs[channel]; } -enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane) +enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane) { return omap_current_dss_features->supported_color_modes[plane]; } EXPORT_SYMBOL(dss_feat_get_supported_color_modes); -enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane) +enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane) { return omap_current_dss_features->overlay_caps[plane]; } -bool dss_feat_color_mode_supported(enum omap_plane plane, +bool dss_feat_color_mode_supported(enum omap_plane_id plane, enum omap_color_mode color_mode) { return omap_current_dss_features->supported_color_modes[plane] & diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index bb4b7f0..603f3ae 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -88,8 +88,8 @@ enum dss_range_param { /* DSS Feature Functions */ unsigned long dss_feat_get_param_min(enum dss_range_param param); unsigned long dss_feat_get_param_max(enum dss_range_param param); -enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane); -bool dss_feat_color_mode_supported(enum omap_plane plane, +enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane); +bool dss_feat_color_mode_supported(enum omap_plane_id plane, enum omap_color_mode color_mode); u32 dss_feat_get_buffer_size_unit(void); /* in bytes */ diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 5b3b961..9b1a55f 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -76,7 +76,7 @@ enum omap_display_type { OMAP_DISPLAY_TYPE_DVI = 1 << 6, }; -enum omap_plane { +enum omap_plane_id { OMAP_DSS_GFX = 0, OMAP_DSS_VIDEO1 = 1, OMAP_DSS_VIDEO2 = 2, @@ -338,7 +338,7 @@ struct omap_overlay { /* static fields */ const char *name; - enum omap_plane id; + enum omap_plane_id id; enum omap_color_mode supported_modes; enum omap_overlay_caps caps; @@ -785,7 +785,7 @@ struct omap_dss_device *omap_dss_find_device(void *data, int dss_feat_get_num_mgrs(void); int dss_feat_get_num_ovls(void); -enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); +enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane); @@ -872,11 +872,12 @@ void dispc_mgr_set_gamma(enum omap_channel channel, const struct drm_color_lut *lut, unsigned int length); -int dispc_ovl_enable(enum omap_plane plane, bool enable); -bool dispc_ovl_enabled(enum omap_plane plane); -void dispc_ovl_set_channel_out(enum omap_plane plane, +int dispc_ovl_enable(enum omap_plane_id plane, bool enable); +bool dispc_ovl_enabled(enum omap_plane_id plane); +void dispc_ovl_set_channel_out(enum omap_plane_id plane, enum omap_channel channel); -int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, +int dispc_ovl_setup(enum omap_plane_id plane, + const struct omap_overlay_info *oi, bool replication, const struct videomode *vm, bool mem_to_mem); enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);