From patchwork Mon Mar 8 18:00:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 84110 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o28I1nXM009621 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 8 Mar 2010 18:02:25 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NohFl-000070-92; Mon, 08 Mar 2010 18:00:29 +0000 Received: from sfi-mx-2.v28.ch3.sourceforge.com ([172.29.28.122] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NohFj-00006t-0h for dri-devel@lists.sourceforge.net; Mon, 08 Mar 2010 18:00:27 +0000 Received-SPF: pass (sfi-mx-2.v28.ch3.sourceforge.com: domain of gmail.com designates 209.85.220.214 as permitted sender) client-ip=209.85.220.214; envelope-from=alexdeucher@gmail.com; helo=mail-fx0-f214.google.com; Received: from mail-fx0-f214.google.com ([209.85.220.214]) by sfi-mx-2.v28.ch3.sourceforge.com with esmtp (Exim 4.69) id 1NohFg-0003qH-DF for dri-devel@lists.sourceforge.net; Mon, 08 Mar 2010 18:00:26 +0000 Received: by fxm6 with SMTP id 6so1911820fxm.2 for ; Mon, 08 Mar 2010 10:00:18 -0800 (PST) MIME-Version: 1.0 Received: by 10.223.7.4 with SMTP id b4mr5887836fab.102.1268071218443; Mon, 08 Mar 2010 10:00:18 -0800 (PST) Date: Mon, 8 Mar 2010 13:00:18 -0500 Message-ID: Subject: [PATCH] drm/radeon/kms: use lcd pll limits when available From: Alex Deucher To: Dave Airlie , DRI Development Mailing List X-Spam-Score: -1.1 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record -0.0 DKIM_VERIFIED Domain Keys Identified Mail: signature passes verification 0.0 DKIM_SIGNED Domain Keys Identified Mail: message has a signature 0.4 AWL AWL: From: address is in the auto white-list X-Headers-End: 1NohFg-0003qH-DF X-BeenThere: dri-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 08 Mar 2010 18:02:25 +0000 (UTC) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 0c67669..a8cd637 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -525,6 +525,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; pll->algo = dig->pll_algo; + pll->flags |= RADEON_PLL_IS_LCD; } } else { if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 6f8619c..2860f05 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -869,6 +869,20 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) p1pll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); + if (crev >= 4) { + p1pll->lcd_pll_out_min = + le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; + if (p1pll->lcd_pll_out_min == 0) + p1pll->lcd_pll_out_min = p1pll->pll_out_min; + p1pll->lcd_pll_out_max = + le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; + if (p1pll->lcd_pll_out_max == 0) + p1pll->lcd_pll_out_max = p1pll->pll_out_max; + } else { + p1pll->lcd_pll_out_min = p1pll->pll_out_min; + p1pll->lcd_pll_out_max = p1pll->pll_out_max; + } + if (p1pll->pll_out_min == 0) { if (ASIC_IS_AVIVO(rdev)) p1pll->pll_out_min = 64800; diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 69af81d..30a84ae 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -633,6 +633,8 @@ bool radeon_combios_get_clock_info(struct drm_device *dev) p1pll->reference_div = RBIOS16(pll_info + 0x10); p1pll->pll_out_min = RBIOS32(pll_info + 0x12); p1pll->pll_out_max = RBIOS32(pll_info + 0x16); + p1pll->lcd_pll_out_min = p1pll->pll_out_min; + p1pll->lcd_pll_out_max = p1pll->pll_out_max; if (rev > 9) { p1pll->pll_in_min = RBIOS32(pll_info + 0x36); diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index e35cc3d..c604810 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -460,10 +460,19 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll, uint32_t best_error = 0xffffffff; uint32_t best_vco_diff = 1; uint32_t post_div; + u32 pll_out_min, pll_out_max; DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); freq = freq * 1000; + if (pll->flags & RADEON_PLL_IS_LCD) { + pll_out_min = pll->lcd_pll_out_min; + pll_out_max = pll->lcd_pll_out_max; + } else { + pll_out_min = pll->pll_out_min; + pll_out_max = pll->pll_out_max; + } + if (pll->flags & RADEON_PLL_USE_REF_DIV) min_ref_div = max_ref_div = pll->reference_div; else { @@ -527,10 +536,10 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll, tmp = (uint64_t)pll->reference_freq * feedback_div; vco = radeon_div(tmp, ref_div); - if (vco < pll->pll_out_min) { + if (vco < pll_out_min) { min_feed_div = feedback_div + 1; continue; - } else if (vco > pll->pll_out_max) { + } else if (vco > pll_out_max) { max_feed_div = feedback_div; continue; } @@ -666,6 +675,15 @@ calc_fb_ref_div(struct radeon_pll *pll, { fixed20_12 ffreq, max_error, error, pll_out, a; u32 vco; + u32 pll_out_min, pll_out_max; + + if (pll->flags & RADEON_PLL_IS_LCD) { + pll_out_min = pll->lcd_pll_out_min; + pll_out_max = pll->lcd_pll_out_max; + } else { + pll_out_min = pll->pll_out_min; + pll_out_max = pll->pll_out_max; + } ffreq.full = rfixed_const(freq); /* max_error = ffreq * 0.0025; */ @@ -677,7 +695,7 @@ calc_fb_ref_div(struct radeon_pll *pll, vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac)); vco = vco / ((*ref_div) * 10); - if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max)) + if ((vco < pll_out_min) || (vco > pll_out_max)) continue; /* pll_out = vco / post_div; */ @@ -705,6 +723,15 @@ static void radeon_compute_pll_new(struct radeon_pll *pll, { u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; u32 best_freq = 0, vco_frequency; + u32 pll_out_min, pll_out_max; + + if (pll->flags & RADEON_PLL_IS_LCD) { + pll_out_min = pll->lcd_pll_out_min; + pll_out_max = pll->lcd_pll_out_max; + } else { + pll_out_min = pll->pll_out_min; + pll_out_max = pll->pll_out_max; + } /* freq = freq / 10; */ do_div(freq, 10); @@ -715,7 +742,7 @@ static void radeon_compute_pll_new(struct radeon_pll *pll, goto done; vco_frequency = freq * post_div; - if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) + if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max)) goto done; if (pll->flags & RADEON_PLL_USE_REF_DIV) { @@ -740,7 +767,7 @@ static void radeon_compute_pll_new(struct radeon_pll *pll, continue; vco_frequency = freq * post_div; - if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) + if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max)) continue; if (pll->flags & RADEON_PLL_USE_REF_DIV) { ref_div = pll->reference_div; diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 1702b82..b868ffa 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -129,6 +129,7 @@ struct radeon_tmds_pll { #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) #define RADEON_PLL_USE_POST_DIV (1 << 12) +#define RADEON_PLL_IS_LCD (1 << 13) /* pll algo */ enum radeon_pll_algo { @@ -149,6 +150,8 @@ struct radeon_pll { uint32_t pll_in_max; uint32_t pll_out_min; uint32_t pll_out_max; + uint32_t lcd_pll_out_min; + uint32_t lcd_pll_out_max; uint32_t best_vco; /* divider limits */