From patchwork Sun Aug 8 05:10:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 12424705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4598EC4320A for ; Sun, 8 Aug 2021 05:11:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2AD760F38 for ; Sun, 8 Aug 2021 05:11:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E2AD760F38 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=goldelico.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B30889D2E; Sun, 8 Aug 2021 05:11:10 +0000 (UTC) Received: from mo4-p04-ob.smtp.rzone.de (mo4-p04-ob.smtp.rzone.de [85.215.255.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78A8A89CC1 for ; Sun, 8 Aug 2021 05:10:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628399450; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=AgNhKnnrM28zue4mAUQn3VQlXQfVMSZE6+Kj8AD2hck=; b=paUoKBoTD+FnyOT6CdORWc51RHSRQjKeW3qR+eKbCchtmlj8HFs74GpMvt+j5qYTMi 05kutkVU+SuDO6tSEbW15Tcb9KroPve7+Qv2piDev6l7wXUBPnTvFQAcLMTWdY8nvqNh PJUiXEsMui/FlWS95bjZkWfkY0cS595qqao+u4OAegUQdqNUvfy50hTs7Ax7nSt9wIQf NzifeEGG7XbM29Xhi66QjK5ttNnf95U/A45VH2/1orplGBZGK15hUP43T7VXY6Tse8FQ WCRB0XQiou+mduAPe+qnmRWko8uWeWo9Y0a7JSCvKpzHDjiOjlg7jAo8hQizkLtBDgcn zqiQ== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdcKVX0" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x785AnEyk (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 8 Aug 2021 07:10:49 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org Subject: [PATCH v3 9/9] drm/ingenic: add some jz4780 specific features Date: Sun, 8 Aug 2021 07:10:43 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Paul Boddie The jz4780 has some features which need initialization according to the vendor kernel. Signed-off-by: Paul Boddie Signed-off-by: H. Nikolaus Schaller --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 33ce3794aa126..f3b1b10bc079b 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -69,6 +69,10 @@ struct jz_soc_info { bool needs_dev_clk; bool has_osd; bool map_noncoherent; + bool has_alpha; + bool has_pcfg; + bool has_recover; + bool has_rgbc; bool use_extended_hwdesc; unsigned int hwdesc_size; unsigned int max_width, max_height; @@ -671,6 +675,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; } + if (priv->soc_info->has_recover) + cfg |= JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN; + /* set use of the 8-word descriptor and OSD foreground usage. */ if (priv->soc_info->use_extended_hwdesc) cfg |= JZ_LCD_CFG_DESCRIPTOR_8; @@ -1208,6 +1215,25 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) if (soc_info->has_osd) regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); + if (soc_info->has_alpha) + regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_ALPHAEN); + + /* Magic values from the vendor kernel for the priority thresholds. */ + if (soc_info->has_pcfg) + regmap_write(priv->map, JZ_REG_LCD_PCFG, + JZ_LCD_PCFG_PRI_MODE | + JZ_LCD_PCFG_HP_BST_16 | + (511 << JZ_LCD_PCFG_THRESHOLD2_OFFSET) | + (400 << JZ_LCD_PCFG_THRESHOLD1_OFFSET) | + (256 << JZ_LCD_PCFG_THRESHOLD0_OFFSET)); + + /* RGB output control may be superfluous. */ + if (soc_info->has_rgbc) + regmap_write(priv->map, JZ_REG_LCD_RGBC, + JZ_LCD_RGBC_RGB_FORMAT_ENABLE | + JZ_LCD_RGBC_ODD_RGB | + JZ_LCD_RGBC_EVEN_RGB); + mutex_init(&priv->clk_mutex); priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; @@ -1355,6 +1381,9 @@ static const struct jz_soc_info jz4740_soc_info = { .needs_dev_clk = true, .has_osd = false, .map_noncoherent = false, + .has_pcfg = false, + .has_recover = false, + .has_rgbc = false, .hwdesc_size = sizeof(struct ingenic_dma_hwdesc), .max_width = 800, .max_height = 600, @@ -1368,6 +1397,9 @@ static const struct jz_soc_info jz4725b_soc_info = { .needs_dev_clk = false, .has_osd = true, .map_noncoherent = false, + .has_pcfg = false, + .has_recover = false, + .has_rgbc = false, .hwdesc_size = sizeof(struct ingenic_dma_hwdesc), .max_width = 800, .max_height = 600, @@ -1382,6 +1414,9 @@ static const struct jz_soc_info jz4770_soc_info = { .needs_dev_clk = false, .has_osd = true, .map_noncoherent = true, + .has_pcfg = false, + .has_recover = false, + .has_rgbc = false, .hwdesc_size = sizeof(struct ingenic_dma_hwdesc), .max_width = 1280, .max_height = 720, @@ -1395,6 +1430,10 @@ static const struct jz_soc_info jz4770_soc_info = { static const struct jz_soc_info jz4780_soc_info = { .needs_dev_clk = true, .has_osd = true, + .has_alpha = true, + .has_pcfg = true, + .has_recover = true, + .has_rgbc = true, .use_extended_hwdesc = true, .hwdesc_size = sizeof(struct ingenic_dma_hwdesc_ext), .max_width = 4096,