From patchwork Fri Apr 21 09:51:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 9692305 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B990960383 for ; Fri, 21 Apr 2017 09:51:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B1EE3223A6 for ; Fri, 21 Apr 2017 09:51:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A6CF628614; Fri, 21 Apr 2017 09:51:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 12DDC223A6 for ; Fri, 21 Apr 2017 09:51:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 275626E418; Fri, 21 Apr 2017 09:51:52 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1190E6E418 for ; Fri, 21 Apr 2017 09:51:50 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v3L9pfeg014738; Fri, 21 Apr 2017 04:51:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1492768301; bh=unFCFE5sNGEeUMv4tlOtWtb9m11jVf1H7slJXJ2mI1g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gWrrrA9/CqtRrNe0nUtuG9rygy4YEaLZo6AnvYFqMZg6OjTSIj99021A9ACH1urZY 3YGol+T9peCvT4yQbp0OUXsHjvJZ63lC1cboRraadXf3nVCl8Q3RbThYWkhaJcRKH9 Iu3ER3+tiBBawJx1BQI5WXT6QTDUxj/8LgaClWno= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3L9pfDX003110; Fri, 21 Apr 2017 04:51:41 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Fri, 21 Apr 2017 04:51:40 -0500 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3L9pNB2015129; Fri, 21 Apr 2017 04:51:39 -0500 From: Jyri Sarha To: Subject: [PATCH RFC 6/6] drm/omap: Enable ycbcr_to_rgb_properties for omapdrm planes REVISIT Date: Fri, 21 Apr 2017 12:51:17 +0300 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 Cc: Liviu.Dudau@arm.com, Jyri Sarha , tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Adds support for YCBCR_TO_RGB_MODE and YCBCR_TO_RGB_CSC properties to omap_plane.c and dispc.c. The supported CSC presets are: - YCbCt BT.601 limited range to RGB BT.601 full range - YCbCt BT.601 full range to RGB BT.601 full range - YCbCt BT.709 limited range to RGB BT.709 full range Custom CSC with YCbCr limited and full range preoffsets are also supported. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/dss/dispc.c | 131 +++++++++++++++++++++++----------- drivers/gpu/drm/omapdrm/dss/omapdss.h | 14 ++++ drivers/gpu/drm/omapdrm/omap_plane.c | 41 +++++++++++ 3 files changed, 144 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index f2a2d08..48dfb9c 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -752,16 +752,6 @@ static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc, } } -struct csc_coef_yuv2rgb { - int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr; - bool full_range; -}; - -struct csc_coef_rgb2yuv { - int yr, yg, yb, cbr, cbg, cbb, crr, crg, crb; - bool full_range; -}; - static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane, const struct csc_coef_yuv2rgb *ct) { @@ -795,6 +785,54 @@ static void dispc_wb_write_color_conv_coef(const struct csc_coef_rgb2yuv *ct) #undef CVAL } +/* YUV -> RGB, ITU-R BT.601, full range */ +const static struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_full = { + 256, 0, 358, /* ry, rcb, rcr |1.000 0.000 1.402|*/ + 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/ + 256, 452, 0, /* by, bcb, bcr |1.000 1.772 0.000|*/ + true, /* full range */ +}; + +/* YUV -> RGB, ITU-R BT.601, limited range */ +const static struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_lim = { + 298, 0, 409, /* ry, rcb, rcr |1.164 0.000 1.596|*/ + 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/ + 298, 516, 0, /* by, bcb, bcr |1.164 2.017 0.000|*/ + false, /* limited range */ +}; + +/* YUV -> RGB, ITU-R BT.709, limited range */ +const static struct csc_coef_yuv2rgb coefs_yuv2rgb_bt709_lim = { + 298, 0, 459, /* ry, rcb, rcr |1.164 0.000 1.793|*/ + 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/ + 298, 541, 0, /* by, bcb, bcr |1.164 2.112 0.000|*/ + false, /* limited range */ +}; + +/* RGB -> YUV, ITU-R BT.601, limited range */ +const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_lim = { + 66, 129, 25, /* yr, yg, yb | 0.257 0.504 0.098|*/ + -38, -74, 112, /* cbr, cbg, cbb |-0.148 -0.291 0.439|*/ + 112, -94, -18, /* crr, crg, crb | 0.439 -0.368 -0.071|*/ + false, /* limited range */ +}; + +/* RGB -> YUV, ITU-R BT.601, full range */ +const static struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_full = { + 77, 150, 29, /* yr, yg, yb | 0.299 0.587 0.114|*/ + -43, -85, 128, /* cbr, cbg, cbb |-0.173 -0.339 0.511|*/ + 128, -107, -21, /* crr, crg, crb | 0.511 -0.428 -0.083|*/ + true, /* full range */ +}; + +/* RGB -> YUV, ITU-R BT.709, limited range */ +const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt701_lim = { + 47, 157, 16, /* yr, yg, yb | 0.1826 0.6142 0.0620|*/ + -26, -87, 112, /* cbr, cbg, cbb |-0.1006 -0.3386 0.4392|*/ + 112, -102, -10, /* crr, crg, crb | 0.4392 -0.3989 -0.0403|*/ + false, /* limited range */ +}; + static void dispc_setup_color_conv_coef(void) { int i; @@ -802,38 +840,6 @@ static void dispc_setup_color_conv_coef(void) /* always use full range for now */ bool use_full_range = true; - /* YUV -> RGB, ITU-R BT.601, limited range */ - const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_lim = { - 298, 0, 409, /* ry, rcb, rcr */ - 298, -100, -208, /* gy, gcb, gcr */ - 298, 516, 0, /* by, bcb, bcr */ - false, /* limited range */ - }; - - /* YUV -> RGB, ITU-R BT.601, full range */ - const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_full = { - 256, 0, 358, /* ry, rcb, rcr */ - 256, -88, -182, /* gy, gcb, gcr */ - 256, 452, 0, /* by, bcb, bcr */ - true, /* full range */ - }; - - /* RGB -> YUV, ITU-R BT.601, limited range */ - const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_lim = { - 66, 129, 25, /* yr, yg, yb */ - -38, -74, 112, /* cbr, cbg, cbb */ - 112, -94, -18, /* crr, crg, crb */ - false, /* limited range */ - }; - - /* RGB -> YUV, ITU-R BT.601, full range */ - const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_full = { - 77, 150, 29, /* yr, yg, yb */ - -43, -85, 128, /* cbr, cbg, cbb */ - 128, -107, -21, /* crr, crg, crb */ - true, /* full range */ - }; - const struct csc_coef_yuv2rgb *yuv2rgb; const struct csc_coef_rgb2yuv *rgb2yuv; @@ -2890,6 +2896,42 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, return 0; } + +static int dispc_ovl_set_csc(enum omap_plane_id plane, + const struct omap_overlay_info *oi) +{ + struct csc_coef_yuv2rgb csc; + const struct csc_coef_yuv2rgb *cscp = &csc; + + switch (oi->ycbcr_to_rgb_mode) { + case DRM_PLANE_YCBCR_TO_RGB_CSC_LIM_PREOFFSET: + csc = oi->ycbcr_to_rgb_csc; + csc.full_range = false; + break; + case DRM_PLANE_YCBCR_TO_RGB_CSC_FULL_PREOFFSET: + csc = oi->ycbcr_to_rgb_csc; + csc.full_range = true; + break; + case DRM_PLANE_YCBCR_BT601_LIM_TO_RGB_BT601_FULL: + cscp = &coefs_yuv2rgb_bt601_lim; + break; + case DRM_PLANE_YCBCR_BT601_FULL_TO_RGB_BT601_FULL: + cscp = &coefs_yuv2rgb_bt601_full; + break; + case DRM_PLANE_YCBCR_BT709_LIM_TO_RGB_BT709_FULL: + cscp = &coefs_yuv2rgb_bt709_lim; + break; + default: + DSSERR("Unsupported CSC mode %d for plane %d\n", + oi->ycbcr_to_rgb_mode, plane); + return -EINVAL; + } + + dispc_ovl_write_color_conv_coef(plane, cscp); + + return 0; +} + static int dispc_ovl_setup(enum omap_plane_id plane, const struct omap_overlay_info *oi, const struct videomode *vm, bool mem_to_mem) @@ -2912,6 +2954,11 @@ static int dispc_ovl_setup(enum omap_plane_id plane, oi->out_width, oi->out_height, oi->color_mode, oi->rotation, oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, oi->rotation_type, replication, vm, mem_to_mem); + if (r) + return r; + + if (dss_feat_color_mode_supported(plane, OMAP_DSS_COLOR_UYVY)) + r = dispc_ovl_set_csc(plane, oi); return r; } diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 63c2684..f4aab99 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -25,6 +25,7 @@ #include