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Fri, 4 Nov 2022 06:47:26 +0000 From: Sandor Yu To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, kishon@ti.com, vkoul@kernel.org Subject: [v2 07/10] dts-bindings: phy: Add Cadence HDP-TX DP PHY bindings Date: Fri, 4 Nov 2022 14:44:57 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: X-ClientProxiedBy: SG2PR06CA0194.apcprd06.prod.outlook.com (2603:1096:4:1::26) To PAXPR04MB9448.eurprd04.prod.outlook.com (2603:10a6:102:2b1::21) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9448:EE_|AM9PR04MB8081:EE_ X-MS-Office365-Filtering-Correlation-Id: 308e741c-a486-4717-3905-08dabe306f0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Sandor Yu --- .../bindings/phy/phy-cadence-hdptx-dp.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-hdptx-dp.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-hdptx-dp.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-hdptx-dp.yaml new file mode 100644 index 000000000000..ab6f4e25c425 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-cadence-hdptx-dp.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/phy-cadence-hdptx-dp.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence HDP(HDMI/DisplayPort) TX PHY for DisplayPort protocol binding + +description: + This binding describes the Cadence HDP-TX PHY for DispalyPort protocol. + +maintainers: + - Sandor Yu + +properties: + compatible: + enum: + - cdns,hdptx-dp-phy + + reg: + description: + Offset of Cadence HDPTX APB configuration registers. + + clocks: + items: + description: + PHY reference clock. Must contain an entry in clock-names. + + clock-names: + items: + - const: refclk + + "#phy-cells": + const: 0 + + cdns,num-lanes: + description: + Number of lanes. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + default: 4 + + cdns,max-bit-rate: + description: + Maximum DisplayPort link bit rate to use, in Mbps + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2160, 2430, 2700, 3240, 4320, 5400] + default: 5400 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + dp_phy: dp_phy@32c00000 { + compatible = "cdns,hdptx-dp-phy"; + reg = <0x32c00000 0x100000>; + #phy-cells = <0>; + clocks = <&hdmi_phy_27m>; + clock-names = "refclk"; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + };