From patchwork Fri Oct 18 18:46:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11200489 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A3A461599 for ; Sun, 20 Oct 2019 00:07:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8BB892064A for ; Sun, 20 Oct 2019 00:07:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8BB892064A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=goldelico.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F67189CAD; Sun, 20 Oct 2019 00:07:00 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mo6-p02-ob.smtp.rzone.de (mo6-p02-ob.smtp.rzone.de [IPv6:2a01:238:20a:202:5302::8]) by gabe.freedesktop.org (Postfix) with ESMTPS id BB3096EBBA for ; Fri, 18 Oct 2019 18:46:47 +0000 (UTC) X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6F3CFF60=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 44.28.1 DYNA|AUTH) with ESMTPSA id R0b2a8v9IIkWDLC (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Fri, 18 Oct 2019 20:46:32 +0200 (CEST) From: "H. Nikolaus Schaller" To: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren Subject: [PATCH 1/7] dt-bindings: gpu: pvrsgx: add initial bindings Date: Fri, 18 Oct 2019 20:46:24 +0200 Message-Id: X-Mailer: git-send-email 2.19.1 In-Reply-To: References: MIME-Version: 1.0 X-Mailman-Approved-At: Sun, 20 Oct 2019 00:06:45 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1571424405; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=iSkqypEOIXqjPnMech7nom91pT488acblcWrfraIbHk=; b=S0o92dELx2JgxFuyzeVh4CxkHCK9MH4nmJHazpFBFpyxbZgjw45vgz9OO8VjaoQRYZ +gdEiARB4Ap4nmj8j/vjgPnTUMJFtBgjzFNx2TLJAw6rEVI0ixzSjLybJYWRov/QT4/L Eqrhg3MGuh+F/ZQZJ81SIKhN6ScAAEa79msI47aQwfAC1QibK7tZPev3HD2JoYgU0x+o fx47VXXZ5eRgTyj6EFnVZzgZmIF5ALWqoaWPTPPu2TQF3cu+EaFp9bdPW1tqhT610nq5 VqM63+I0Oco5ZIEpD5z8L4SEut2qrG+jHHs/NPY/ANXFomndLWcCq1Oz5OpFo78Ej710 GL5A== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-omap@vger.kernel.org, "H. Nikolaus Schaller" , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@pyra-handheld.com, letux-kernel@openphoenux.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo and others. Here we describe how the SGX processor is interfaced to the SoC (registers, interrupt etc.). Clock, Reset and power management should be handled by the parent node. Signed-off-by: H. Nikolaus Schaller --- .../devicetree/bindings/gpu/img,pvrsgx.txt | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.txt diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.txt b/Documentation/devicetree/bindings/gpu/img,pvrsgx.txt new file mode 100644 index 000000000000..4ad87c075791 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.txt @@ -0,0 +1,76 @@ +Imagination PVR/SGX GPU + +Only the Imagination SGX530, SGX540 and SGX544 GPUs are currently covered by this binding. + +Required properties: +- compatible: Should be one of + "img,sgx530-121", "img,sgx530", "ti,omap-omap3-sgx530-121"; + - BeagleBoard ABC, OpenPandora 600MHz + "img,sgx530-125", "img,sgx530", "ti,omap-omap3-sgx530-125"; + - BeagleBoard XM, GTA04, OpenPandora 1GHz + "img,sgx530-125", "img,sgx530", "ti,omap-am3517-sgx530-125"; + "img,sgx530-125", "img,sgx530", "ti,omap-am335x-sgx530-125"; + - BeagleBone Black + "img,sgx540-120", "img,sgx540", "ti,omap-omap4-sgx540-120"; + - Pandaboard (ES) + "img,sgx544-112", "img,sgx544", "ti,omap-omap4-sgx544-112"; + "img,sgx544-116", "img,sgx544", "ti,omap-omap5-sgx544-116"; + - OMAP5 UEVM, Pyra Handheld + "img,sgx544-116", "img,sgx544", "ti,omap-dra7-sgx544-116"; + + For further study: + "ti,omap-am3517-sgx530-?" + "ti,omap-am43xx-sgx530-?" + "ti,ti43xx-sgx" + "ti,ti81xx-sgx" + "img,jz4780-sgx5??-?" + "intel,poulsbo-sgx?" + "intel,cedarview-sgx?" + "sunxi,sgx-544-?" - Banana-Pi-M3 (Allwinner A83T) + + The "ti,omap..." entries are needed temporarily to handle SoC + specific builds of the kernel module. + + In the long run, only the "img,sgx..." entry should suffice + to match a generic driver for all architectures and driver + code can dynamically find out on which SoC it is running. + + +- reg: Physical base addresses and lengths of the register areas. +- reg-names: Names for the register areas. +- interrupts: The interrupt numbers. + +Optional properties: +- timer: the timer to be used by the driver. +- img,cores: number of cores. Defaults to <1>. + +/ { + ocp { + sgx_module: target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + + sgx@fe00 { + compatible = "img,sgx544-116", "img,sgx544", "ti,omap-omap5-sgx544-116"; + reg = <0xfe00 0x200>; + reg-names = "sgx"; + interrupts = ; + timer = <&timer11>; + img,cores = <2>; + }; + }; + }; +};