[0/4] address several S32G2/S32G3 SoC based boards particularities

Message ID	20240705134647.3524969-1-ciprianmarian.costea@oss.nxp.com (mailing list archive)
Headers	show Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2041.outbound.protection.outlook.com [40.107.104.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 636B814AD1A for <imx@lists.linux.dev>; Fri, 5 Jul 2024 13:47:23 +0000 (UTC) From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com> To: Haibo Chen <haibo.chen@nxp.com>, Adrian Hunter <adrian.hunter@intel.com>, Ulf Hansson <ulf.hansson@linaro.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com> Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, s32@nxp.com, Ciprian Costea <ciprianmarian.costea@oss.nxp.com> Subject: [PATCH 0/4] address several S32G2/S32G3 SoC based boards particularities Date: Fri, 5 Jul 2024 16:46:43 +0300 Message-ID: <20240705134647.3524969-1-ciprianmarian.costea@oss.nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1
Series	address several S32G2/S32G3 SoC based boards particularities \| expand [0/4] address several S32G2/S32G3 SoC based boards particularities [1/4] mmc: sdhci-esdhc-imx: disable card detect wake for S32G based platforms [2/4] mmc: sdhci-esdhc-imx: obtain the 'per' clock rate after its enablement [3/4] mmc: sdhci-esdhc-imx: add option to not change pinctrl state in suspend [4/4] MAINTAINERS: add 's32@nxp.com' as relevant mailing list for 'sdhci-esdhc-imx' driver

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20240705134647.3524969-1-ciprianmarian.costea@oss.nxp.com (mailing list archive)

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From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
To: Haibo Chen <haibo.chen@nxp.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>
Cc: linux-kernel@vger.kernel.org,
	linux-mmc@vger.kernel.org,
	imx@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org,
	s32@nxp.com,
	Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
Subject: [PATCH 0/4] address several S32G2/S32G3 SoC based boards
 particularities
Date: Fri,  5 Jul 2024 16:46:43 +0300
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Series

address several S32G2/S32G3 SoC based boards particularities | expand

Message

Ciprian Marian Costea July 5, 2024, 1:46 p.m. UTC

This patchset addresses several S32G2/S32G3 SoC based boards
uSDHC controller particularities such as:
- GPIO card detect wake mechanism is not available
- Changing the pinctrl state in suspend routine is not supported

It also fixes a clocking usage issue on 'clk_get_rate',
in case of 'per' clock.

Ciprian Costea (4):
  mmc: sdhci-esdhc-imx: disable card detect wake for S32G based
    platforms
  mmc: sdhci-esdhc-imx: obtain the 'per' clock rate after its enablement
  mmc: sdhci-esdhc-imx: add option to not change pinctrl state in
    suspend
  MAINTAINERS: add 's32@nxp.com' as relevant mailing list for
    'sdhci-esdhc-imx' driver

 MAINTAINERS                        |  1 +
 drivers/mmc/host/sdhci-esdhc-imx.c | 28 ++++++++++++++++++++++------
 2 files changed, 23 insertions(+), 6 deletions(-)