| Message ID | 20250128-pci_fixup_addr-v9-0-3c4bb506f665@nxp.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: dwc: opitimaze RC Host/EP pci_fixup_addr() | expand |
Hello Frank, Typo in subject: s/opitimaze/optimize/ On Tue, Jan 28, 2025 at 05:07:33PM -0500, Frank Li wrote: > > Bjorn's comments in https://lore.kernel.org/imx/20250123190900.GA650360@bhelgaas/ > > > After all cpu_address_fixup() removed, we can remove use_parent_dt_ranges > > in one clean up patches. > > > > > ... > > dw_pcie_rd_other_conf > > dw_pcie_wr_other_conf > > dw_pcie_prog_outbound_atu() only called if pp->cfg0_io_shared, > > after an ECAM map via dw_pcie_other_conf_map_bus() and subsequent > > successful access; atu.cpu_addr came from pp->io_base, set by > > dw_pcie_host_init() from pci_pio_to_address(), which I'm pretty > > sure returns a CPU address. > > io_base is parent_bus_address > > > So this still looks wrong to me. In addition, I think doing the > > ATU setup in *_map() and restore in *rd/wr_other_conf() is ugly > > and looks unreliable. > > .... > > > dw_pcie_pme_turn_off > > atu.cpu_addr came from pp.msg_res, set by > > dw_pcie_host_request_msg_tlp_res() to a CPU address at the end of > > the first MMIO bridge window. This one also looks wrong to me. > > Fixed at this version. I feel like it would have been easier if you replied to Bjorn's comments directly in the thread instead of pasting them here (to a cover letter). Please don't shoot the messenger, but I don't see any reply to (what I assume is the biggest reason why Bjorn did not merge this series): "" .cpu_addr_fixup() is a generic problem that affects dwc (dra7xx, imx6, artpec6, intel-gw, visconti), cadence (cadence-plat), and now apparently microchip. I deferred these because I'm hoping we can come up with a more generic solution that's easier to apply across all these cases. I don't really want to merge something that immediately needs to be reworked for other drivers. "" It should probably state in the cover letter how v9 addresses Bjorn's concern when it comes to other PCI controller drivers, especially those that are not DWC based. Kind regards, Niklas
On Wed, Jan 29, 2025 at 11:13:42AM +0100, Niklas Cassel wrote: > Hello Frank, > > Typo in subject: > s/opitimaze/optimize/ > > > On Tue, Jan 28, 2025 at 05:07:33PM -0500, Frank Li wrote: > > > > Bjorn's comments in https://lore.kernel.org/imx/20250123190900.GA650360@bhelgaas/ > > > > > After all cpu_address_fixup() removed, we can remove use_parent_dt_ranges > > > in one clean up patches. > > > > > > > > ... > > > dw_pcie_rd_other_conf > > > dw_pcie_wr_other_conf > > > dw_pcie_prog_outbound_atu() only called if pp->cfg0_io_shared, > > > after an ECAM map via dw_pcie_other_conf_map_bus() and subsequent > > > successful access; atu.cpu_addr came from pp->io_base, set by > > > dw_pcie_host_init() from pci_pio_to_address(), which I'm pretty > > > sure returns a CPU address. > > > > io_base is parent_bus_address > > > > > So this still looks wrong to me. In addition, I think doing the > > > ATU setup in *_map() and restore in *rd/wr_other_conf() is ugly > > > and looks unreliable. > > > > .... > > > > > dw_pcie_pme_turn_off > > > atu.cpu_addr came from pp.msg_res, set by > > > dw_pcie_host_request_msg_tlp_res() to a CPU address at the end of > > > the first MMIO bridge window. This one also looks wrong to me. > > > > Fixed at this version. > > > I feel like it would have been easier if you replied to Bjorn's comments > directly in the thread instead of pasting them here (to a cover letter). > > > Please don't shoot the messenger, but I don't see any reply to (what I > assume is the biggest reason why Bjorn did not merge this series): > > "" > .cpu_addr_fixup() is a generic problem that affects dwc (dra7xx, imx6, > artpec6, intel-gw, visconti), cadence (cadence-plat), and now > apparently microchip. > > I deferred these because I'm hoping we can come up with a more generic > solution that's easier to apply across all these cases. I don't > really want to merge something that immediately needs to be reworked > for other drivers. > "" > > It should probably state in the cover letter how v9 addresses Bjorn's > concern when it comes to other PCI controller drivers, especially those > that are not DWC based. Thank you for your reminder, I forget mentions this in cover letter. I create new patch to figure out this Bjorn's problem. PCI: Add parent_bus_offset to resource_entry With above patch, other platform will be easy apply the same method. Frank > > > Kind regards, > Niklas
Hello Frank, On Wed, Jan 29, 2025 at 10:28:23AM -0500, Frank Li wrote: > On Wed, Jan 29, 2025 at 11:13:42AM +0100, Niklas Cassel wrote: > > > > Please don't shoot the messenger, but I don't see any reply to (what I > > assume is the biggest reason why Bjorn did not merge this series): > > > > "" > > .cpu_addr_fixup() is a generic problem that affects dwc (dra7xx, imx6, > > artpec6, intel-gw, visconti), cadence (cadence-plat), and now > > apparently microchip. > > > > I deferred these because I'm hoping we can come up with a more generic > > solution that's easier to apply across all these cases. I don't > > really want to merge something that immediately needs to be reworked > > for other drivers. > > "" > > > > It should probably state in the cover letter how v9 addresses Bjorn's > > concern when it comes to other PCI controller drivers, especially those > > that are not DWC based. > > Thank you for your reminder, I forget mentions this in cover letter. I > create new patch to figure out this Bjorn's problem. > > PCI: Add parent_bus_offset to resource_entry I see. If you are solving this problem in a generic way, then it would make sense if the generic patch comes first in the series, and then the driver (DWC) specific patches come after that. Your cover letter, including the subject is also written in a DWC specific manner. If you are solving a generic problem, then describe first how you solve the generic problem, followed by DWC specific details. See e.g. my cover letter here: https://lore.kernel.org/linux-pci/20250119050850.2kogtpl5hatpp2tv@thinkpad/T/#t Kind regards, Niklas
On Wed, Jan 29, 2025 at 05:39:18PM +0100, Niklas Cassel wrote: > Hello Frank, > > On Wed, Jan 29, 2025 at 10:28:23AM -0500, Frank Li wrote: > > On Wed, Jan 29, 2025 at 11:13:42AM +0100, Niklas Cassel wrote: > > > > > > Please don't shoot the messenger, but I don't see any reply to (what I > > > assume is the biggest reason why Bjorn did not merge this series): > > > > > > "" > > > .cpu_addr_fixup() is a generic problem that affects dwc (dra7xx, imx6, > > > artpec6, intel-gw, visconti), cadence (cadence-plat), and now > > > apparently microchip. > > > > > > I deferred these because I'm hoping we can come up with a more generic > > > solution that's easier to apply across all these cases. I don't > > > really want to merge something that immediately needs to be reworked > > > for other drivers. > > > "" > > > > > > It should probably state in the cover letter how v9 addresses Bjorn's > > > concern when it comes to other PCI controller drivers, especially those > > > that are not DWC based. > > > > Thank you for your reminder, I forget mentions this in cover letter. I > > create new patch to figure out this Bjorn's problem. > > > > PCI: Add parent_bus_offset to resource_entry > > I see. > > If you are solving this problem in a generic way, then it would make sense > if the generic patch comes first in the series, and then the driver (DWC) > specific patches come after that. > > Your cover letter, including the subject is also written in a DWC specific > manner. > > If you are solving a generic problem, then describe first how you solve > the generic problem, followed by DWC specific details. > > See e.g. my cover letter here: > https://lore.kernel.org/linux-pci/20250119050850.2kogtpl5hatpp2tv@thinkpad/T/#t Thanks, let's wait for Bjorn's comments about new method. I will do that next time if need respin. Frank > > > Kind regards, > Niklas
== RC side: ┌─────────┐ ┌────────────┐ ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ 0x7ff8_0000─┼───┘ │ │ │ │ │ │ │ │ │ │ │ │ │ PCI Addr 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► │ │ │ │ │ 0 0x7000_0000─┼────────►├─────────┐ │ │ │ └─────────┘ │ └──────► CfgSpace ─┼────────────► BUS Fabric │ │ │ 0 │ │ │ └──────────► MemSpace ─┼────────────► IA: 0x8000_0000 │ │ 0x8000_0000 └────────────┘ Current dwc implimemnt, pci_fixup_addr() call back is needed when bus fabric convert cpu address before send to PCIe controller. bus@5f000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; Device tree already can descript all address translate. Some hardware driver implement fixup function by mask some bits of cpu address. Last pci-imx6.c are little bit better by fetch memory resource's offset to do fixup. static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) { ... entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); return cpu_addr - entry->offset; } But it is not good by using IORESOURCE_MEM to fix up io/cfg address map although address translate is the same as IORESOURCE_MEM. This patches to fetch untranslate range information for PCIe controller (pcie@5f010000: ranges). So current config ATU without cpu_fixup_addr(). == EP side: Endpoint ┌───────────────────────────────────────────────┐ │ pcie-ep@5f010000 │ │ ┌────────────────┐│ │ │ Endpoint ││ │ │ PCIe ││ │ │ Controller ││ │ bus@5f000000 │ ││ │ ┌──────────┐ │ ││ │ │ │ Outbound Transfer ││ │┌─────┐ │ Bus ┼─────►│ ATU ──────────┬┬─────► ││ │ │ Fabric │Bus │ ││PCI Addr ││ CPU ├───►│ │Addr │ ││0xA000_0000 ││ │CPU │ │0x8000_0000 ││ │└─────┘Addr└──────────┘ │ ││ │ 0x7000_0000 └────────────────┘│ └───────────────────────────────────────────────┘ bus@5f000000 { compatible = "simple-bus"; ranges = <0x80000000 0x0 0x70000000 0x10000000>; pcie-ep@5f010000 { reg = <0x5f010000 0x00010000>, <0x80000000 0x10000000>; reg-names = "dbi", "addr_space"; ... ^^^^ }; ... }; Add `bus_addr_base` to configure the outbound window address for CPU write. The BUS fabric generally passes the same address to the PCIe EP controller, but some BUS fabrics convert the address before sending it to the PCIe EP controller. Above diagram, CPU write data to outbound windows address 0x7000_0000, Bus fabric convert it to 0x8000_0000. ATU should use BUS address 0x8000_0000 as input address and convert to PCI address 0xA000_0000. Previously, `cpu_addr_fixup()` was used to handle address conversion. Now, the device tree provides this information. The both pave the road to eliminate ugle cpu_fixup_addr() callback function. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- Changes in v9: - There are some change in patches, if need drop review-tags, let me known. - DTS part: https://lore.kernel.org/imx/20250128211559.1582598-2-Frank.Li@nxp.com/T/#u - Keep "use_parent_dt_ranges" flags because need below combine logic cpu_addr_fixup use_parent_dt_ranges NULL X No difference. !NULL true Use device tree parent_address informaion [1] !NULL false Keep use lagency method [2] Generally DTS is in different maintainer tree. It need two steps to cleanup cpu_address_fixup() to avoid function block. 1. Update dts, which reflect the correct bus fabric behavior. 2. set "use_parent_dt_ranges" to true, then remove "cpu_address_fixup()" callback in platform driver. Bjorn's comments in https://lore.kernel.org/imx/20250123190900.GA650360@bhelgaas/ > After all cpu_address_fixup() removed, we can remove use_parent_dt_ranges > in one clean up patches. > > ... > dw_pcie_rd_other_conf > dw_pcie_wr_other_conf > dw_pcie_prog_outbound_atu() only called if pp->cfg0_io_shared, > after an ECAM map via dw_pcie_other_conf_map_bus() and subsequent > successful access; atu.cpu_addr came from pp->io_base, set by > dw_pcie_host_init() from pci_pio_to_address(), which I'm pretty > sure returns a CPU address. io_base is parent_bus_address > So this still looks wrong to me. In addition, I think doing the > ATU setup in *_map() and restore in *rd/wr_other_conf() is ugly > and looks unreliable. .... > dw_pcie_pme_turn_off > atu.cpu_addr came from pp.msg_res, set by > dw_pcie_host_request_msg_tlp_res() to a CPU address at the end of > the first MMIO bridge window. This one also looks wrong to me. Fixed at this version. - Link to v8: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-0-c4bfa5193288@nxp.com Changes in v8: - Add mani's review tages - use rename use_dt_ranges to use_parent_dt_ranges - Add dev_warn_once to reminder to fix their dt file and remove cpu_fixup_addr() callback. - rename dw_pcie_get_untranslate_addr() to dw_pcie_get_parent_addr() - Link to v7: https://lore.kernel.org/r/20241029-pci_fixup_addr-v7-0-8310dc24fb7c@nxp.com Changes in v7: - fix | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/ - Link to v6: https://lore.kernel.org/r/20241028-pci_fixup_addr-v6-0-ebebcd8fd4ff@nxp.com Changes in v6: - merge RC and EP to one thread! - Link to v5: https://lore.kernel.org/r/20241015-pci_fixup_addr-v5-0-ced556c85270@nxp.com Changes in v5: - update address order in diagram patches. - remove confused 0x5f00_0000 range - update patch1's commit message. - Link to v4: https://lore.kernel.org/r/20241008-pci_fixup_addr-v4-0-25e5200657bc@nxp.com Changes in v4: - Improve commit message by add driver source code path. - Link to v3: https://lore.kernel.org/r/20240930-pci_fixup_addr-v3-0-80ee70352fc7@nxp.com Changes in v3: - see each patch - Link to v2: https://lore.kernel.org/r/20240926-pci_fixup_addr-v2-0-e4524541edf4@nxp.com Changes in v2: - see each patch - Link to v1: https://lore.kernel.org/r/20240924-pci_fixup_addr-v1-0-57d14a91ec4f@nxp.com --- Frank Li (7): PCI: dwc: Use resource start as iomap() input in dw_pcie_pme_turn_off() PCI: dwc: Rename cpu_addr to parent_bus_addr for ATU configuration PCI: Add parent_bus_offset to resource_entry PCI: dwc: Use devicetree 'ranges' property to get rid of cpu_addr_fixup() callback PCI: dwc: ep: Add parent_bus_addr for outbound window PCI: dwc: ep: Ensure proper iteration over outbound map windows PCI: imx6: Remove cpu_addr_fixup() drivers/pci/bus.c | 11 +++++- drivers/pci/controller/dwc/pci-imx6.c | 18 +-------- drivers/pci/controller/dwc/pcie-designware-ep.c | 29 +++++++++++--- drivers/pci/controller/dwc/pcie-designware-host.c | 46 +++++++++++++++++++---- drivers/pci/controller/dwc/pcie-designware.c | 43 ++++++++++++--------- drivers/pci/controller/dwc/pcie-designware.h | 11 +++++- drivers/pci/of.c | 12 +++++- include/linux/pci.h | 2 + include/linux/resource_ext.h | 1 + 9 files changed, 121 insertions(+), 52 deletions(-) --- base-commit: 5fcc194143ce5918ea0790a16323a844c5ab9499 change-id: 20240924-pci_fixup_addr-a8568f9bbb34 Best regards, --- Frank Li <Frank.Li@nxp.com>