diff mbox series

[v4,2/6] dt-bindindgs: clock: nxp: support i.MX95 Camera CSR module

Message ID 20240314-imx95-blk-ctl-v4-2-d23de23b6ff2@nxp.com (mailing list archive)
State Superseded
Headers show
Series Add support i.MX95 BLK CTL module clock features | expand

Commit Message

Peng Fan (OSS) March 14, 2024, 1:25 p.m. UTC 
From: Peng Fan <peng.fan@nxp.com>

The i.MX95 Camera CSR is a set of registers that provides various
configuration and status of the Camera modules’ operations. Registers
are available to enable clock gating to the ISP and CSI-2 pixel
formatters, enable transport of various pixel data and non-pixel data
types, control their routing, and other functions. Status registers
provide pixel data type error information and pending transaction
from Camera NoC initiators.

This patch is to add clock features for Camera CSR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../bindings/clock/nxp,imx95-camera-csr.yaml       | 50 ++++++++++++++++++++++
 include/dt-bindings/clock/nxp,imx95-clock.h        |  7 +++
 2 files changed, 57 insertions(+)

Comments

Rob Herring (Arm) March 15, 2024, 5:24 p.m. UTC | #1 
On Thu, Mar 14, 2024 at 09:25:11PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> The i.MX95 Camera CSR is a set of registers that provides various
> configuration and status of the Camera modules’ operations. Registers
> are available to enable clock gating to the ISP and CSI-2 pixel
> formatters, enable transport of various pixel data and non-pixel data
> types, control their routing, and other functions. Status registers
> provide pixel data type error information and pending transaction
> from Camera NoC initiators.
> 
> This patch is to add clock features for Camera CSR.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../bindings/clock/nxp,imx95-camera-csr.yaml       | 50 ++++++++++++++++++++++
>  include/dt-bindings/clock/nxp,imx95-clock.h        |  7 +++
>  2 files changed, 57 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml
> new file mode 100644
> index 000000000000..e62494e3a8b1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/nxp,imx95-camera-csr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX95 Camera MIX Block Control
> +
> +maintainers:
> +  - Peng Fan <peng.fan@nxp.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: nxp,imx95-camera-csr
> +      - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +    description:
> +      The clock consumer should specify the desired clock by having the clock
> +      ID in its "clocks" phandle cell. See
> +      include/dt-bindings/clock/nxp,imx95-clock.h
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    syscon@4c410000 {
> +      compatible = "nxp,imx95-camera-csr", "syscon";
> +      reg = <0x4ac10000 0x10000>;
> +      #clock-cells = <1>;
> +      clocks = <&scmi_clk 62>;
> +      power-domains = <&scmi_devpd 3>;
> +    };
> +...
> diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h
> index 9d8f0a6d12d0..c671c4dbb4d5 100644
> --- a/include/dt-bindings/clock/nxp,imx95-clock.h
> +++ b/include/dt-bindings/clock/nxp,imx95-clock.h
> @@ -11,4 +11,11 @@
>  #define IMX95_CLK_VPUBLK_JPEG_DEC		2
>  #define IMX95_CLK_VPUBLK_END			3
>  
> +#define IMX95_CLK_CAMBLK_CSI2_FOR0		0
> +#define IMX95_CLK_CAMBLK_CSI2_FOR1		1
> +#define IMX95_CLK_CAMBLK_ISP_AXI		2
> +#define IMX95_CLK_CAMBLK_ISP_PIXEL		3
> +#define IMX95_CLK_CAMBLK_ISP			4
> +#define IMX95_CLK_CAMBLK_END			5

Same issue here. With that dropped,

Reviewed-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml
new file mode 100644
index 000000000000..e62494e3a8b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml
@@ -0,0 +1,50 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nxp,imx95-camera-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX95 Camera MIX Block Control
+
+maintainers:
+  - Peng Fan <peng.fan@nxp.com>
+
+properties:
+  compatible:
+    items:
+      - const: nxp,imx95-camera-csr
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      The clock consumer should specify the desired clock by having the clock
+      ID in its "clocks" phandle cell. See
+      include/dt-bindings/clock/nxp,imx95-clock.h
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@4c410000 {
+      compatible = "nxp,imx95-camera-csr", "syscon";
+      reg = <0x4ac10000 0x10000>;
+      #clock-cells = <1>;
+      clocks = <&scmi_clk 62>;
+      power-domains = <&scmi_devpd 3>;
+    };
+...
diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h
index 9d8f0a6d12d0..c671c4dbb4d5 100644
--- a/include/dt-bindings/clock/nxp,imx95-clock.h
+++ b/include/dt-bindings/clock/nxp,imx95-clock.h
@@ -11,4 +11,11 @@ 
 #define IMX95_CLK_VPUBLK_JPEG_DEC		2
 #define IMX95_CLK_VPUBLK_END			3
 
+#define IMX95_CLK_CAMBLK_CSI2_FOR0		0
+#define IMX95_CLK_CAMBLK_CSI2_FOR1		1
+#define IMX95_CLK_CAMBLK_ISP_AXI		2
+#define IMX95_CLK_CAMBLK_ISP_PIXEL		3
+#define IMX95_CLK_CAMBLK_ISP			4
+#define IMX95_CLK_CAMBLK_END			5
+
 #endif	/* __DT_BINDINGS_CLOCK_IMX95_H */