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Thu, 14 Mar 2024 13:17:36 +0000 From: "Peng Fan (OSS)" Date: Thu, 14 Mar 2024 21:25:11 +0800 Subject: [PATCH v4 2/6] dt-bindindgs: clock: nxp: support i.MX95 Camera CSR module Message-Id: <20240314-imx95-blk-ctl-v4-2-d23de23b6ff2@nxp.com> References: <20240314-imx95-blk-ctl-v4-0-d23de23b6ff2@nxp.com> In-Reply-To: <20240314-imx95-blk-ctl-v4-0-d23de23b6ff2@nxp.com> To: Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1710422742; l=2772; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=P7z0swJT7PRGt/RAmx6moPJ3qMxKqwVy0GrmLcELtcw=; b=5u7Yb9YrFBzedC1TznEgaM0eVWCsRQDuxosTAGj7Bw/saNz7EMUD1LM7GIUm1R+s2zdyvnhgs 8UrdFAG831dDqgoJyheT9fBVtvrDk69JW9CQL0rr2iIvGB8y1BwieGR X-Developer-Key: i=peng.fan@nxp.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?Ow7r5lJ//vFfYPY3rpDE8HU+GaWX?= =?utf-8?q?gCWDfnR/u9K2MM94Ed1RQrI9Uq5p08j+9UN3gKxd4EeRHAi6HXu7Ekzn7uBpnqEhH?= =?utf-8?q?MvayMsRcMmAhyWc4OewjpMUlpkeRIAJ7SNnVrBe6+bL2xS8BuyAVZekIIv9yu8gQX?= =?utf-8?q?Fw2cO61+NYqxN4XQejWFtpGZX4kqZhpd5FDoi3Xr6mlgQH8+WPGWIPEKOQhJXfSdt?= =?utf-8?q?fe7Xvf8TTZRFvFDC7Xega4V/fZFhlJyxXZwMEXtbTC0kaVWMiX9KBqzeY0lT456nv?= =?utf-8?q?SH04hvyXx4SfbbxK+9uSVxTFbimYEu803iX5DTw+84Bw6+T8TkFQ5bA9hGMLgGyXX?= =?utf-8?q?oPEZTdVIsRMepvvch4A5XT1Ve9Jq+VmUNvVoOd3WmugK5VmrkbO7f5Cc/ZlMIF6vp?= =?utf-8?q?rkwhM6sDbhHLFKMIkVXpJbrnvVqSLkL3TbcL8bkFq4qVVoOL2HqcLIi5Mz8M7eWr/?= =?utf-8?q?SuuoVR6bOorirUrJs/mRO1vY8d5VgCtPnHJe5UFpq7dpIsBFLGsMaVuQOFtxpOYO4?= =?utf-8?q?rk8U9fVZj9rNcNvfotcOpJ7xfOXEH2L2pnezdmN+4aHKPHnzqlj6QdgwwHMp9TU3x?= =?utf-8?q?yG7iRlxu2BB+PD8u1cK3FnqWCyj51qPxjPOYl3eIvKKmOKeYrC/iDfeBSmMVpTp0G?= =?utf-8?q?YHYtsepWWN6elKGos6DswuxXimCGJHf5ciLoWzxHO7Z1suhHHVV23SETlEYfKUHjm?= =?utf-8?q?SNirNYEjld463NMizDQulTo5W3BRKs5Txz+QRi7uxzlIztnqEcscz4AzOOwU26FW7?= =?utf-8?q?FaqcYe4V4TGpwfG6Np2YzZpdYB4CmsRZAv0/UfWrzXllvU53uKp+7wohaRrp3mZX5?= =?utf-8?q?KR5uZCXBY5UzliHk9IgqbO3AqayArlBAM8kRoiL1ZkZ7WKNcxl/MnN3HkbxSJgvNZ?= =?utf-8?q?lZva7tkCihRvMfzFYpCrKUYQdhZUGv9Q41xUoxo0l9AgMyhdTa57f98kD+RFH1/Fh?= =?utf-8?q?1WJ0D/iRGnmAxgbIZ5LpsDWCBD9DKT+JaTKzP+xc7gO8o5DAFdKsdlZ/TD2D8Ma0J?= =?utf-8?q?wf5csuNtjovH7PxXOYWCoiCg4cVzIpi/Wt5TX7dXruslOTC1GNs/f2btnhgElKWof?= =?utf-8?q?GPLxnqUrA2nfzBGhIcWl9HxoSLxlSPzBk7fyXD7fIwafJHQCug2gigMWRXTCKEpyj?= =?utf-8?q?55eNCTebE1M0fxmSaC+5Mn8rk6+B82tAnxE7+Liog3WVRcg1C8kEt8I8Pu4PBD0LI?= =?utf-8?q?Fy28leqjj5OyX/7dcMLqaE+GM6/mu2w6azRykHqiccWbHLe2Ys/Tv/Ddnqznck0Ty?= =?utf-8?q?3r1lBF5aBEOfi9jQ3l9MRsGye/DBxkGCe8MWvgrfGqAyBoFAAXQLHayucPhe24CTS?= =?utf-8?q?bZnSFs5sYK0lfOql3cXDQ5UEfyi7LhE9OG7uk4c/R1j4mHPBLd7bPGCoGP8WJxD8P?= =?utf-8?q?fxgigpXM1XtsrIXbOOh8m61ZnVi7tC8/mDqd9h4u9OVE/Xuivx4zF9SQyPmHLQUJD?= =?utf-8?q?A6MSSNgyWUBrRLbdH9LuGYhYSj+HMDgrqnH7JM2h+9wtTEGCC/5JgHJCZoVRrOC0L?= =?utf-8?q?owRTtXfkwdPm?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 82be0c0c-f619-421a-2717-08dc44291deb X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2024 13:17:36.7241 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: uR4QpvTvjokPyDySxkkFyoct6WRqFmo0S4ZWuZq2vZwA2kMymmJ+aacirDruLTtnJdD4XmJiySQGt79BtECJJQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8806 From: Peng Fan The i.MX95 Camera CSR is a set of registers that provides various configuration and status of the Camera modules’ operations. Registers are available to enable clock gating to the ISP and CSI-2 pixel formatters, enable transport of various pixel data and non-pixel data types, control their routing, and other functions. Status registers provide pixel data type error information and pending transaction from Camera NoC initiators. This patch is to add clock features for Camera CSR. Signed-off-by: Peng Fan Reviewed-by: Rob Herring --- .../bindings/clock/nxp,imx95-camera-csr.yaml | 50 ++++++++++++++++++++++ include/dt-bindings/clock/nxp,imx95-clock.h | 7 +++ 2 files changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml new file mode 100644 index 000000000000..e62494e3a8b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-camera-csr.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nxp,imx95-camera-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX95 Camera MIX Block Control + +maintainers: + - Peng Fan + +properties: + compatible: + items: + - const: nxp,imx95-camera-csr + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See + include/dt-bindings/clock/nxp,imx95-clock.h + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + syscon@4c410000 { + compatible = "nxp,imx95-camera-csr", "syscon"; + reg = <0x4ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&scmi_clk 62>; + power-domains = <&scmi_devpd 3>; + }; +... diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h index 9d8f0a6d12d0..c671c4dbb4d5 100644 --- a/include/dt-bindings/clock/nxp,imx95-clock.h +++ b/include/dt-bindings/clock/nxp,imx95-clock.h @@ -11,4 +11,11 @@ #define IMX95_CLK_VPUBLK_JPEG_DEC 2 #define IMX95_CLK_VPUBLK_END 3 +#define IMX95_CLK_CAMBLK_CSI2_FOR0 0 +#define IMX95_CLK_CAMBLK_CSI2_FOR1 1 +#define IMX95_CLK_CAMBLK_ISP_AXI 2 +#define IMX95_CLK_CAMBLK_ISP_PIXEL 3 +#define IMX95_CLK_CAMBLK_ISP 4 +#define IMX95_CLK_CAMBLK_END 5 + #endif /* __DT_BINDINGS_CLOCK_IMX95_H */