[v8,7/8] perf vendor events arm64:: Add i.MX95 DDR Performance Monitor metrics

Message ID	20240322063930.749126-7-xu.yang_2@nxp.com (mailing list archive)
State	Superseded
Headers	show Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2041.outbound.protection.outlook.com [40.107.7.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 249FF17580 for <imx@lists.linux.dev>; Fri, 22 Mar 2024 06:39:57 +0000 (UTC) From: Xu Yang <xu.yang_2@nxp.com> To: frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v8 7/8] perf vendor events arm64:: Add i.MX95 DDR Performance Monitor metrics Date: Fri, 22 Mar 2024 14:39:29 +0800 Message-Id: <20240322063930.749126-7-xu.yang_2@nxp.com> In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com> References: <20240322063930.749126-1-xu.yang_2@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk MIME-Version: 1.0
Series	[v8,1/8] dt-bindings: perf: fsl-imx-ddr: Add i.MX95 compatible \| expand [v8,1/8] dt-bindings: perf: fsl-imx-ddr: Add i.MX95 compatible [v8,2/8] perf: imx_perf: add macro definitions for parsing config attr [v8,3/8] perf: imx_perf: let the driver manage the counter usage rather the user [v8,4/8] perf: imx_perf: refactor driver for imx93 [v8,5/8] perf: imx_perf: fix counter start and config sequence [v8,6/8] perf: imx_perf: add support for i.MX95 platform [v8,7/8] perf vendor events arm64:: Add i.MX95 DDR Performance Monitor metrics [v8,8/8] perf vendor events arm64:: Add i.MX93 DDR Performance Monitor metrics

diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json new file mode 100644 index 000000000000..4dc9d2968bdc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json @@ -0,0 +1,9 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx95_ddr.cycles", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json new file mode 100644 index 000000000000..a3ae787d448c --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json @@ -0,0 +1,778 @@ +[ + { + "BriefDescription": "bandwidth usage for lpddr5 evk board", + "MetricName": "imx95_bandwidth_usage.lpddr5", + "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)", + "ScaleUnit": "1e2%", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters read from ddr", + "MetricName": "imx95_ddr_read.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters write to ddr", + "MetricName": "imx95_ddr_write.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 read from ddr", + "MetricName": "imx95_ddr_read.a55_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 write to ddr (part1)", + "MetricName": "imx95_ddr_write.a55_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 write to ddr (part2)", + "MetricName": "imx95_ddr_write.a55_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 read from ddr", + "MetricName": "imx95_ddr_read.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 write to ddr", + "MetricName": "imx95_ddr_write.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 read from ddr", + "MetricName": "imx95_ddr_read.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 write to ddr", + "MetricName": "imx95_ddr_write.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 read from ddr", + "MetricName": "imx95_ddr_read.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 write to ddr", + "MetricName": "imx95_ddr_write.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 read from ddr", + "MetricName": "imx95_ddr_read.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 write to ddr", + "MetricName": "imx95_ddr_write.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 read from ddr", + "MetricName": "imx95_ddr_read.a55_4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 write to ddr", + "MetricName": "imx95_ddr_write.a55_4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 5 read from ddr", + "MetricName": "imx95_ddr_read.a55_5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 5 write to ddr", + "MetricName": "imx95_ddr_write.a55_5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr", + "MetricName": "imx95_ddr_read.cortexa_dsu_l3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr", + "MetricName": "imx95_ddr_write.cortexa_dsu_l3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m33 read from ddr", + "MetricName": "imx95_ddr_read.m33", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m33 write to ddr", + "MetricName": "imx95_ddr_write.m33", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m7 read from ddr", + "MetricName": "imx95_ddr_read.m7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m7 write to ddr", + "MetricName": "imx95_ddr_write.m7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of sentinel read from ddr", + "MetricName": "imx95_ddr_read.sentinel", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of sentinel write to ddr", + "MetricName": "imx95_ddr_write.sentinel", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma1 read from ddr", + "MetricName": "imx95_ddr_read.edma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma1 write to ddr", + "MetricName": "imx95_ddr_write.edma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma2 read from ddr", + "MetricName": "imx95_ddr_read.edma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma2 write to ddr", + "MetricName": "imx95_ddr_write.edma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of netc read from ddr", + "MetricName": "imx95_ddr_read.netc", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of netc write to ddr", + "MetricName": "imx95_ddr_write.netc", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of npu read from ddr", + "MetricName": "imx95_ddr_read.npu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of npu write to ddr", + "MetricName": "imx95_ddr_write.npu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of gpu read from ddr", + "MetricName": "imx95_ddr_read.gpu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of gpu write to ddr", + "MetricName": "imx95_ddr_write.gpu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc1 read from ddr", + "MetricName": "imx95_ddr_read.usdhc1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc1 write to ddr", + "MetricName": "imx95_ddr_write.usdhc1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc2 read from ddr", + "MetricName": "imx95_ddr_read.usdhc2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc2 write to ddr", + "MetricName": "imx95_ddr_write.usdhc2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc3 read from ddr", + "MetricName": "imx95_ddr_read.usdhc3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc3 write to ddr", + "MetricName": "imx95_ddr_write.usdhc3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of xspi read from ddr", + "MetricName": "imx95_ddr_read.xspi", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of xspi write to ddr", + "MetricName": "imx95_ddr_write.xspi", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie1 read from ddr", + "MetricName": "imx95_ddr_read.pcie1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie1 write to ddr", + "MetricName": "imx95_ddr_write.pcie1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie2 read from ddr", + "MetricName": "imx95_ddr_read.pcie2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie2 write to ddr", + "MetricName": "imx95_ddr_write.pcie2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie3 read from ddr", + "MetricName": "imx95_ddr_read.pcie3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie3 write to ddr", + "MetricName": "imx95_ddr_write.pcie3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie4 read from ddr", + "MetricName": "imx95_ddr_read.pcie4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie4 write to ddr", + "MetricName": "imx95_ddr_write.pcie4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb1 read from ddr", + "MetricName": "imx95_ddr_read.usb1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb1 write to ddr", + "MetricName": "imx95_ddr_write.usb1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb2 read from ddr", + "MetricName": "imx95_ddr_read.usb2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb2 write to ddr", + "MetricName": "imx95_ddr_write.usb2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec primary bus read from ddr", + "MetricName": "imx95_ddr_read.vpu_primy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec primary bus write to ddr", + "MetricName": "imx95_ddr_write.vpu_primy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec secondary bus read from ddr", + "MetricName": "imx95_ddr_read.vpu_secndy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec secondary bus write to ddr", + "MetricName": "imx95_ddr_write.vpu_secndy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg decoder read from ddr", + "MetricName": "imx95_ddr_read.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg decoder write to ddr", + "MetricName": "imx95_ddr_write.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg encoder read from ddr", + "MetricName": "imx95_ddr_read.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg encoder write to ddr", + "MetricName": "imx95_ddr_write.jpeg_enc", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all vpu submodules read from ddr", + "MetricName": "imx95_ddr_read.vpu_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all vpu submodules write to ddr", + "MetricName": "imx95_ddr_write.vpu_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of cortex m0+ read from ddr", + "MetricName": "imx95_ddr_read.m0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of cortex m0+ write to ddr", + "MetricName": "imx95_ddr_write.m0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of camera edma read from ddr", + "MetricName": "imx95_ddr_read.camera_edma", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of camera edma write to ddr", + "MetricName": "imx95_ddr_write.camera_edma", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd read from ddr", + "MetricName": "imx95_ddr_read.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd write to ddr", + "MetricName": "imx95_ddr_write.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules read from ddr", + "MetricName": "imx95_ddr_read.camera_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part1)", + "MetricName": "imx95_ddr_write.camera_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part2)", + "MetricName": "imx95_ddr_write.camera_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part3)", + "MetricName": "imx95_ddr_write.camera_all_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter store read from ddr", + "MetricName": "imx95_ddr_read.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter write to ddr", + "MetricName": "imx95_ddr_write.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer read from ddr", + "MetricName": "imx95_ddr_read.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer write to ddr", + "MetricName": "imx95_ddr_write.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules read from ddr", + "MetricName": "imx95_ddr_read.disp_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules write to ddr (part1)", + "MetricName": "imx95_ddr_write.disp_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules write to ddr (part2)", + "MetricName": "imx95_ddr_write.disp_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index e42efc16723e..ac9b7ca41856 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -284,6 +284,7 @@ class JsonEvent: 'hisi_sccl,hha': 'hisi_sccl,hha', 'hisi_sccl,l3c': 'hisi_sccl,l3c', 'imx8_ddr': 'imx8_ddr', + 'imx9_ddr': 'imx9_ddr', 'L3PMC': 'amd_l3', 'DFPMC': 'amd_df', 'UMCPMC': 'amd_umc',

[v8,7/8] perf vendor events arm64:: Add i.MX95 DDR Performance Monitor metrics

Commit Message

Patch