| Message ID | 20240402-pci2_upstream-v3-10-803414bdb430@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: imx6: Fix\rename\clean up and add lut information for imx95 | expand |
On Tue, Apr 02, 2024 at 10:33:46AM -0400, Frank Li wrote: > From: Richard Zhu <hongxing.zhu@nxp.com> > > Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. > > Add "fsl,local-address" property for i.MX8Q platforms. fsl,local-address > is address of PCIe module in high speed io (HSIO)subsystem bus fabric. HSIO > bus fabric convert the incoming address base to this local-address. Two > instances of PCI have difference local address. This is just some intermediate bus address? We really should be able to describe this with standard ranges properties. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > .../devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml | 5 +++++ > .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 18 ++++++++++++++++++ > 2 files changed, 23 insertions(+)
On Mon, Apr 29, 2024 at 10:48:23AM -0500, Rob Herring wrote: > On Tue, Apr 02, 2024 at 10:33:46AM -0400, Frank Li wrote: > > From: Richard Zhu <hongxing.zhu@nxp.com> > > > > Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. > > > > Add "fsl,local-address" property for i.MX8Q platforms. fsl,local-address > > is address of PCIe module in high speed io (HSIO)subsystem bus fabric. HSIO > > bus fabric convert the incoming address base to this local-address. Two > > instances of PCI have difference local address. > > This is just some intermediate bus address? We really should be able to > describe this with standard ranges properties. Yes, Maybe dwc's implement have some problem. After read below doc again https://elinux.org/Device_Tree_Usage#PCI_Address_Translation ┌──────┐ ┌──────────┐ ┌────┐0x18001000 │ │ │ │ │CPU ├───────────►│ ├──┤ Others │ └────┘ │ │ │ │ │ │ └──────────┘ │ │ │ │ ┌─────────┐ │ │ │ │ ┌───────────┐ │ ├──►│ HSIO │ 0xB8001000 ├───────────┤ │ │ │ Fabric ├───────────►│Bar0 │ TLP mem 0xB8001000 │ │ │ │ │0xB8000000 ├───────► └──────┘ └─────────┘ │ │ Main Fabric ├───────────┤ │ │ │ │ │ │ │ │ │ │ │ │ │ DWC │ │ PCIe │ │ Controller│ │ │ │ │ └───────────┘ dts should be ranges = <0x82000000 0 0xB8000000 0x18000000 0 0x07f00000> ^^^^ u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) offset = entry->res->start; { ... return (cpu_addr - entry->offset); } NVME can work. let me do more test. Frank > > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > .../devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml | 5 +++++ > > .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 18 ++++++++++++++++++ > > 2 files changed, 23 insertions(+)
On Mon, Apr 29, 2024 at 05:23:23PM -0400, Frank Li wrote: > On Mon, Apr 29, 2024 at 10:48:23AM -0500, Rob Herring wrote: > > On Tue, Apr 02, 2024 at 10:33:46AM -0400, Frank Li wrote: > > > From: Richard Zhu <hongxing.zhu@nxp.com> > > > > > > Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. > > > > > > Add "fsl,local-address" property for i.MX8Q platforms. fsl,local-address > > > is address of PCIe module in high speed io (HSIO)subsystem bus fabric. HSIO > > > bus fabric convert the incoming address base to this local-address. Two > > > instances of PCI have difference local address. > > > > This is just some intermediate bus address? We really should be able to > > describe this with standard ranges properties. > > Yes, Maybe dwc's implement have some problem. After read below doc again > https://elinux.org/Device_Tree_Usage#PCI_Address_Translation > > ┌──────┐ ┌──────────┐ > ┌────┐0x18001000 │ │ │ │ > │CPU ├───────────►│ ├──┤ Others │ > └────┘ │ │ │ │ > │ │ └──────────┘ > │ │ > │ │ ┌─────────┐ > │ │ │ │ ┌───────────┐ > │ ├──►│ HSIO │ 0xB8001000 ├───────────┤ > │ │ │ Fabric ├───────────►│Bar0 │ TLP mem 0xB8001000 > │ │ │ │ │0xB8000000 ├───────► > └──────┘ └─────────┘ │ │ Note the 0xB8xxxxxxx address on the right is a PCI address which could be anything though folks often make it 1:1. > Main Fabric ├───────────┤ > │ │ > │ │ > │ │ > │ │ > │ │ > │ │ > │ DWC │ > │ PCIe │ > │ Controller│ > │ │ > │ │ > └───────────┘ > > > dts should be > > ranges = <0x82000000 0 0xB8000000 0x18000000 0 0x07f00000> > ^^^^ And HSIO needs a node with ranges = <0xb8000000 0x18000000 size>; Rob
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index a8b34f58f8f49..9e767695d6480 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -92,6 +92,11 @@ properties: enum: [1, 2, 3, 4] default: 1 + fsl,local-address: + description: Specify the local address mapped by the HSIO bus fabric + for i.MX8QM and i.MX8QXP PCIe module. + $ref: /schemas/types.yaml#/definitions/uint32 + phys: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 8b8d77b1154b5..b73218933b80a 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -30,6 +30,7 @@ properties: - fsl,imx8mm-pcie - fsl,imx8mp-pcie - fsl,imx95-pcie + - fsl,imx8q-pcie clocks: minItems: 3 @@ -184,6 +185,23 @@ allOf: - const: pcie_bus - const: pcie_aux + - if: + properties: + compatible: + enum: + - fsl,imx8q-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: dbi + - const: mstr + - const: slv + required: + - fsl,local-address + unevaluatedProperties: false examples: