| Message ID | 20240412222857.3873079-1-robh@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage | expand |
Am Samstag, 13. April 2024, 00:28:51 CEST schrieb Rob Herring: > The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, > it doesn't provide any detail on uarch specific events. > > There's still remaining cases for CPUs without any corresponding PMU > definition and for big.LITTLE systems which only have a single PMU node > (there should be one per core type). > > Signed-off-by: Rob Herring <robh@kernel.org> > --- > SoC Maintainers, Can you please apply this directly. > --- > arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +- > diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi > index 62af0cb94839..734f87db4d11 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi > @@ -141,7 +141,7 @@ cpu_b3: cpu@103 { > }; > > arm-pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, For Rockchip: Acked-by: Heiko Stuebner <heiko@sntech.de>
On Fri, Apr 12, 2024 at 05:28:51PM -0500, Rob Herring wrote: > The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, > it doesn't provide any detail on uarch specific events. > > There's still remaining cases for CPUs without any corresponding PMU > definition and for big.LITTLE systems which only have a single PMU node > (there should be one per core type). > > Signed-off-by: Rob Herring <robh@kernel.org> > --- > SoC Maintainers, Can you please apply this directly. > --- > arch/arm/boot/dts/broadcom/bcm2711.dtsi | 4 ++-- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- > arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +- > arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +- > arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- > arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 2 +- > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 7 +++++++ > arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 7 +++++++ > arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 5 ----- > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +- > arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 +- > arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- > arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- > arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +- > arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +- > arch/arm64/boot/dts/sprd/sc9860.dtsi | 2 +- > arch/arm64/boot/dts/sprd/sc9863a.dtsi | 2 +- > arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 2 +- > arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- > 32 files changed, 44 insertions(+), 35 deletions(-) > [...] > diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts > index 8db4243a4947..9115c99d0dc0 100644 > --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts > +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts > @@ -102,7 +102,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; > }; (For vexpress related change) Acked-by: Sudeep Holla <sudeep.holla@arm.com> -- Regards, Sudeep
Il 13/04/24 00:28, Rob Herring ha scritto: > The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, > it doesn't provide any detail on uarch specific events. > > There's still remaining cases for CPUs without any corresponding PMU > definition and for big.LITTLE systems which only have a single PMU node > (there should be one per core type). > > Signed-off-by: Rob Herring <robh@kernel.org> For MediaTek: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On 4/12/24 17:28, Rob Herring wrote: > The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, > it doesn't provide any detail on uarch specific events. > > There's still remaining cases for CPUs without any corresponding PMU > definition and for big.LITTLE systems which only have a single PMU node > (there should be one per core type). > > Signed-off-by: Rob Herring <robh@kernel.org> > --- > SoC Maintainers, Can you please apply this directly. > --- > arch/arm/boot/dts/broadcom/bcm2711.dtsi | 4 ++-- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- > arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +- > arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +- > arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- > arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 2 +- > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 7 +++++++ > arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 7 +++++++ > arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 5 ----- > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +- > arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 +- > arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- For SoCFPGA, Acked-by: Dinh Nguyen <dinguyen@kernel.org>
> -----Original Message----- > > The "arm,armv8-pmuv3" compatible is intended only for s/w models. > Primarily, it doesn't provide any detail on uarch specific events. > > There's still remaining cases for CPUs without any corresponding PMU > definition and for big.LITTLE systems which only have a single PMU node > (there should be one per core type). > > Signed-off-by: Rob Herring <robh@kernel.org> > --- > SoC Maintainers, Can you please apply this directly. > --- > arch/arm/boot/dts/broadcom/bcm2711.dtsi | 4 ++-- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- > arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +- > arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +- > arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- > arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 2 +- > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 7 +++++++ > arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 7 +++++++ > arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 5 ----- > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +- > arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 +- > arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- > arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- > arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +- > arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +- > arch/arm64/boot/dts/sprd/sc9860.dtsi | 2 +- > arch/arm64/boot/dts/sprd/sc9863a.dtsi | 2 +- > arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 2 +- > arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- For FSD SoC, Acked-by: Alim Akhtar <alim.akhtar@samsung.com>
On Fri, Apr 12, 2024 at 05:28:51PM -0500, Rob Herring wrote: [..] > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- Acked-by: Bjorn Andersson <andersson@kernel.org> Regards, Bjorn
On 4/12/2024 3:28 PM, Rob Herring wrote: > The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, > it doesn't provide any detail on uarch specific events. > > There's still remaining cases for CPUs without any corresponding PMU > definition and for big.LITTLE systems which only have a single PMU node > (there should be one per core type). > > Signed-off-by: Rob Herring <robh@kernel.org> > --- > SoC Maintainers, Can you please apply this directly. > --- > arch/arm/boot/dts/broadcom/bcm2711.dtsi | 4 ++-- > arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- > arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- For the above: Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
On Mon, 15 Apr 2024 at 16:46, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > On Fri, Apr 12, 2024 at 05:28:51PM -0500, Rob Herring wrote: > [..] > > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- > > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- > > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > > arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- > > Acked-by: Bjorn Andersson <andersson@kernel.org> Note, we'd need to override PMU compatibles in sdm636.dtsi and sdm660.dtsi. Ideally it should come as the same patch. > > Regards, > Bjorn >
On Mon, Apr 15, 2024 at 11:52 AM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On Mon, 15 Apr 2024 at 16:46, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > > > On Fri, Apr 12, 2024 at 05:28:51PM -0500, Rob Herring wrote: > > [..] > > > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- > > > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- > > > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > > > arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- > > > > Acked-by: Bjorn Andersson <andersson@kernel.org> > > Note, we'd need to override PMU compatibles in sdm636.dtsi and > sdm660.dtsi. Ideally it should come as the same patch. Uh, that's an A for reuse, but an F for readability... It's sdm632 as well. Will drop sdm630. Rob
On Mon, Apr 15, 2024 at 12:05 PM Rob Herring <robh@kernel.org> wrote: > > On Mon, Apr 15, 2024 at 11:52 AM Dmitry Baryshkov > <dmitry.baryshkov@linaro.org> wrote: > > > > On Mon, 15 Apr 2024 at 16:46, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > > > > > On Fri, Apr 12, 2024 at 05:28:51PM -0500, Rob Herring wrote: > > > [..] > > > > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- > > > > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- > > > > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > > > > arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- > > > > > > Acked-by: Bjorn Andersson <andersson@kernel.org> > > > > Note, we'd need to override PMU compatibles in sdm636.dtsi and > > sdm660.dtsi. Ideally it should come as the same patch. > > Uh, that's an A for reuse, but an F for readability... It's sdm632 as > well. Will drop sdm630. Actually, aren't those Kryo cores just Cortex-A53 derivatives? So the A53 PMU compatible is an improvement over the generic one still. We can't just add kryo260-pmu compatibles because that breaks compatibility. We could have a fallback, but then that introduces a pattern we don't want. Rob
On Mon, 15 Apr 2024 at 20:15, Rob Herring <robh@kernel.org> wrote: > > On Mon, Apr 15, 2024 at 12:05 PM Rob Herring <robh@kernel.org> wrote: > > > > On Mon, Apr 15, 2024 at 11:52 AM Dmitry Baryshkov > > <dmitry.baryshkov@linaro.org> wrote: > > > > > > On Mon, 15 Apr 2024 at 16:46, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > > > > > > > On Fri, Apr 12, 2024 at 05:28:51PM -0500, Rob Herring wrote: > > > > [..] > > > > > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- > > > > > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- > > > > > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > > > > > arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- > > > > > > > > Acked-by: Bjorn Andersson <andersson@kernel.org> > > > > > > Note, we'd need to override PMU compatibles in sdm636.dtsi and > > > sdm660.dtsi. Ideally it should come as the same patch. > > > > Uh, that's an A for reuse, but an F for readability... It's sdm632 as > > well. Will drop sdm630. > > Actually, aren't those Kryo cores just Cortex-A53 derivatives? So the > A53 PMU compatible is an improvement over the generic one still. We > can't just add kryo260-pmu compatibles because that breaks > compatibility. We could have a fallback, but then that introduces a > pattern we don't want. I think it is believed that Gold cores are A73-derivatives.
On 4/15/24 19:41, Dmitry Baryshkov wrote: > On Mon, 15 Apr 2024 at 20:15, Rob Herring <robh@kernel.org> wrote: >> >> On Mon, Apr 15, 2024 at 12:05 PM Rob Herring <robh@kernel.org> wrote: >>> >>> On Mon, Apr 15, 2024 at 11:52 AM Dmitry Baryshkov >>> <dmitry.baryshkov@linaro.org> wrote: >>>> >>>> On Mon, 15 Apr 2024 at 16:46, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: >>>>> >>>>> On Fri, Apr 12, 2024 at 05:28:51PM -0500, Rob Herring wrote: >>>>> [..] >>>>>> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- >>>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- >>>>>> arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- >>>>>> arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- >>>>> >>>>> Acked-by: Bjorn Andersson <andersson@kernel.org> >>>> >>>> Note, we'd need to override PMU compatibles in sdm636.dtsi and >>>> sdm660.dtsi. Ideally it should come as the same patch. >>> >>> Uh, that's an A for reuse, but an F for readability... It's sdm632 as >>> well. Will drop sdm630. >> >> Actually, aren't those Kryo cores just Cortex-A53 derivatives? So the >> A53 PMU compatible is an improvement over the generic one still. We >> can't just add kryo260-pmu compatibles because that breaks >> compatibility. We could have a fallback, but then that introduces a >> pattern we don't want. > > I think it is believed that Gold cores are A73-derivatives. 8xA53 on 630 4xA53+4xA73 on 636/660 Konrad
On Fri, Apr 12, 2024 at 05:28:51PM -0500, Rob Herring wrote: > The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, > it doesn't provide any detail on uarch specific events. > > There's still remaining cases for CPUs without any corresponding PMU > definition and for big.LITTLE systems which only have a single PMU node > (there should be one per core type). > > Signed-off-by: Rob Herring <robh@kernel.org> > --- > SoC Maintainers, Can you please apply this directly. > --- > arch/arm/boot/dts/broadcom/bcm2711.dtsi | 4 ++-- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- > arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +- > arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +- > arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- > arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 2 +- > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- > arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 7 +++++++ > arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 7 +++++++ > arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 5 ----- > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +- > arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 +- > arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- > arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- > arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +- > arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +- > arch/arm64/boot/dts/sprd/sc9860.dtsi | 2 +- > arch/arm64/boot/dts/sprd/sc9863a.dtsi | 2 +- > arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 2 +- For synaptics SoC: Reviewed-by: Jisheng Zhang <jszhang@kernel.org> > arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- > 32 files changed, 44 insertions(+), 35 deletions(-) > > diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi > index 22c7f1561344..926f87b86590 100644 > --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi > +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi > @@ -432,8 +432,8 @@ emmc2: mmc@7e340000 { > }; > }; > > - arm-pmu { > - compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; > + pmu { > + compatible = "arm,cortex-a72-pmu"; > interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > index 072fe20cfca0..cbbc53c47921 100644 > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > @@ -79,7 +79,7 @@ fpga-region { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <0 170 4>, > <0 171 4>, > <0 172 4>, > diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi > index dbf2dce8d1d6..dbe21d88a29e 100644 > --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi > +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi > @@ -106,7 +106,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a57-pmu"; > interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi > index 988928c60f15..ee3f838b4904 100644 > --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi > +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi > @@ -122,7 +122,7 @@ timer { > }; > > pmu { > - compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; > + compatible = "apm,potenza-pmu"; > interrupts = <1 12 0xff04>; > }; > > diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts > index 8db4243a4947..9115c99d0dc0 100644 > --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts > +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts > @@ -102,7 +102,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; > }; > diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi > index 896d1f33b5b6..cfd9fd23a1c2 100644 > --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi > +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi > @@ -102,7 +102,7 @@ IRQ_TYPE_LEVEL_LOW)>, > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a57-pmu"; > interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi > index d8516ec0dae7..857fa427e195 100644 > --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi > +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi > @@ -142,7 +142,7 @@ psci { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a72-pmu"; > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > index 8ad31dee11a3..4c9f1f808427 100644 > --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > @@ -361,7 +361,7 @@ timer { > }; > > pmu { > - compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; > + compatible = "cavium,thunder-pmu"; > interrupts = <1 7 4>; > }; > > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > index 3419bd252696..68cb3d01187a 100644 > --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > @@ -83,7 +83,7 @@ timer { > }; > > pmu { > - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > + compatible = "brcm,vulcan-pmu"; > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > }; > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi > index fe9093b3c02e..a0f7bbd691a0 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi > @@ -81,7 +81,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > index d333b773bc45..8ee6d8c0ef61 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > @@ -276,7 +276,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <0 106 0x4>, > <0 107 0x4>, > <0 95 0x4>, > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > index 1aa38ed09aa4..8352197cea6f 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi > @@ -12,6 +12,13 @@ > #include <dt-bindings/clock/fsl,qoriq-clockgen.h> > #include "fsl-ls208xa.dtsi" > > +/ { > + pmu { > + compatible = "arm,cortex-a57-pmu"; > + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ > + }; > +}; > + > &cpu { > cpu0: cpu@0 { > device_type = "cpu"; > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi > index 8581ea55d254..245bbd615c81 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi > @@ -12,6 +12,13 @@ > #include <dt-bindings/clock/fsl,qoriq-clockgen.h> > #include "fsl-ls208xa.dtsi" > > +/ { > + pmu { > + compatible = "arm,cortex-a72-pmu"; > + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ > + }; > +}; > + > &cpu { > cpu0: cpu@0 { > device_type = "cpu"; > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi > index 0b7292835906..ccba0a135b24 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi > @@ -247,11 +247,6 @@ timer: timer { > <1 10 4>; /* Hypervisor PPI, active-low */ > }; > > - pmu { > - compatible = "arm,armv8-pmuv3"; > - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ > - }; > - > psci { > compatible = "arm,psci-0.2"; > method = "smc"; > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > index a0674c5c5576..b8abd98bdc43 100644 > --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > @@ -104,7 +104,7 @@ dsp_reserved: dsp@92400000 { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a35-pmu"; > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi > index 781761d2942b..ae00e9e54e82 100644 > --- a/arch/arm64/boot/dts/intel/keembay-soc.dtsi > +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi > @@ -70,7 +70,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi > index 76aafa172eb0..2a5eeb21da47 100644 > --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi > @@ -80,7 +80,7 @@ fpga-region { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > index 5591939e057b..75377c292bcb 100644 > --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > @@ -68,7 +68,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a55-pmu"; > interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi > index 1cc3fa1c354d..9603223dd761 100644 > --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi > @@ -68,7 +68,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi > index 9cbd6dd8f671..d0b03dc4d3f4 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi > @@ -165,7 +165,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a35-pmu"; > interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, > <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, > <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, > diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi > index 47f8268e46bf..882b1d1f4ada 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi > @@ -2004,7 +2004,7 @@ L2: l2-cache { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a57-pmu"; > interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > index 89beac833d43..d3cd68190a17 100644 > --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > @@ -165,7 +165,7 @@ memory@40000000 { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > index 832f472c4b7a..f2a5e2e40461 100644 > --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -177,7 +177,7 @@ memory@80000000 { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a55-pmu"; > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi > index f5921b80ef94..349c8ba06aca 100644 > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi > @@ -352,7 +352,7 @@ opp-262500000 { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > index 7dbdf8ca6de6..b74cf4baedd6 100644 > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > @@ -224,7 +224,7 @@ memory@80000000 { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a55-pmu"; > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > }; > > diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi > index 34802cc62983..e57317a17aa9 100644 > --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi > +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi > @@ -109,7 +109,7 @@ timer { > }; > > arm_pmu: pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a55-pmu"; > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; > interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, > <&cpu3>, <&cpu4>, <&cpu5>; > diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi > index 62af0cb94839..734f87db4d11 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi > @@ -141,7 +141,7 @@ cpu_b3: cpu@103 { > }; > > arm-pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi > index e27eb3ed1d47..6bfdbdb0e1cd 100644 > --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi > +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi > @@ -165,7 +165,7 @@ timer { > }; > > pmu { > - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi > index 22d81ace740a..53e5b77d70b5 100644 > --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi > +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi > @@ -134,7 +134,7 @@ timer { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a55-pmu"; > interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi > index 53d616c3cfed..71e4bfcc9e81 100644 > --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi > +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi > @@ -88,7 +88,7 @@ osc: osc { > }; > > pmu { > - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi > index 047a83cee603..690b4ed9c29b 100644 > --- a/arch/arm64/boot/dts/tesla/fsd.dtsi > +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi > @@ -304,7 +304,7 @@ CPU_SLEEP: cpu-sleep { > }; > > arm-pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a72-pmu"; > interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 25d20d803230..34d0e0be3fe6 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -169,7 +169,7 @@ dcc: dcc { > }; > > pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupt-parent = <&gic>; > interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > -- > 2.43.0 >
diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi index 22c7f1561344..926f87b86590 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -432,8 +432,8 @@ emmc2: mmc@7e340000 { }; }; - arm-pmu { - compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; + pmu { + compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 072fe20cfca0..cbbc53c47921 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -79,7 +79,7 @@ fpga-region { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 170 4>, <0 171 4>, <0 172 4>, diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index dbf2dce8d1d6..dbe21d88a29e 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -106,7 +106,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 988928c60f15..ee3f838b4904 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -122,7 +122,7 @@ timer { }; pmu { - compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; + compatible = "apm,potenza-pmu"; interrupts = <1 12 0xff04>; }; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 8db4243a4947..9115c99d0dc0 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -102,7 +102,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 896d1f33b5b6..cfd9fd23a1c2 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -102,7 +102,7 @@ IRQ_TYPE_LEVEL_LOW)>, }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index d8516ec0dae7..857fa427e195 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -142,7 +142,7 @@ psci { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index 8ad31dee11a3..4c9f1f808427 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -361,7 +361,7 @@ timer { }; pmu { - compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; + compatible = "cavium,thunder-pmu"; interrupts = <1 7 4>; }; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi index 3419bd252696..68cb3d01187a 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -83,7 +83,7 @@ timer { }; pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + compatible = "brcm,vulcan-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index fe9093b3c02e..a0f7bbd691a0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -81,7 +81,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d333b773bc45..8ee6d8c0ef61 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -276,7 +276,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 106 0x4>, <0 107 0x4>, <0 95 0x4>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 1aa38ed09aa4..8352197cea6f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -12,6 +12,13 @@ #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include "fsl-ls208xa.dtsi" +/ { + pmu { + compatible = "arm,cortex-a57-pmu"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; +}; + &cpu { cpu0: cpu@0 { device_type = "cpu"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 8581ea55d254..245bbd615c81 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -12,6 +12,13 @@ #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include "fsl-ls208xa.dtsi" +/ { + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; +}; + &cpu { cpu0: cpu@0 { device_type = "cpu"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 0b7292835906..ccba0a135b24 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -247,11 +247,6 @@ timer: timer { <1 10 4>; /* Hypervisor PPI, active-low */ }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ - }; - psci { compatible = "arm,psci-0.2"; method = "smc"; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index a0674c5c5576..b8abd98bdc43 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -104,7 +104,7 @@ dsp_reserved: dsp@92400000 { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi index 781761d2942b..ae00e9e54e82 100644 --- a/arch/arm64/boot/dts/intel/keembay-soc.dtsi +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -70,7 +70,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 76aafa172eb0..2a5eeb21da47 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -80,7 +80,7 @@ fpga-region { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 5591939e057b..75377c292bcb 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -68,7 +68,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 1cc3fa1c354d..9603223dd761 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -68,7 +68,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 9cbd6dd8f671..d0b03dc4d3f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -165,7 +165,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 47f8268e46bf..882b1d1f4ada 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2004,7 +2004,7 @@ L2: l2-cache { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 89beac833d43..d3cd68190a17 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -165,7 +165,7 @@ memory@40000000 { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 832f472c4b7a..f2a5e2e40461 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -177,7 +177,7 @@ memory@80000000 { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index f5921b80ef94..349c8ba06aca 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -352,7 +352,7 @@ opp-262500000 { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 7dbdf8ca6de6..b74cf4baedd6 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -224,7 +224,7 @@ memory@80000000 { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 34802cc62983..e57317a17aa9 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -109,7 +109,7 @@ timer { }; arm_pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 62af0cb94839..734f87db4d11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -141,7 +141,7 @@ cpu_b3: cpu@103 { }; arm-pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index e27eb3ed1d47..6bfdbdb0e1cd 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -165,7 +165,7 @@ timer { }; pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index 22d81ace740a..53e5b77d70b5 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -134,7 +134,7 @@ timer { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index 53d616c3cfed..71e4bfcc9e81 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -88,7 +88,7 @@ osc: osc { }; pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 047a83cee603..690b4ed9c29b 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -304,7 +304,7 @@ CPU_SLEEP: cpu-sleep { }; arm-pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 25d20d803230..34d0e0be3fe6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -169,7 +169,7 @@ dcc: dcc { }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, it doesn't provide any detail on uarch specific events. There's still remaining cases for CPUs without any corresponding PMU definition and for big.LITTLE systems which only have a single PMU node (there should be one per core type). Signed-off-by: Rob Herring <robh@kernel.org> --- SoC Maintainers, Can you please apply this directly. --- arch/arm/boot/dts/broadcom/bcm2711.dtsi | 4 ++-- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +- arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 2 +- arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 5 ----- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +- arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +- arch/arm64/boot/dts/sprd/sc9860.dtsi | 2 +- arch/arm64/boot/dts/sprd/sc9863a.dtsi | 2 +- arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 2 +- arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 32 files changed, 44 insertions(+), 35 deletions(-)