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Fri, 19 Apr 2024 03:29:26 +0000 From: "Peng Fan (OSS)" Date: Fri, 19 Apr 2024 11:36:59 +0800 Subject: [PATCH v2 04/12] arm64: dts: imx93: assign usdhc[1..3] root clock to 400MHz Message-Id: <20240419-imx93-dts-4-13-v2-4-9076e1d7d399@nxp.com> References: <20240419-imx93-dts-4-13-v2-0-9076e1d7d399@nxp.com> In-Reply-To: <20240419-imx93-dts-4-13-v2-0-9076e1d7d399@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan , Haibo Chen , Sherry Sun X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713497841; l=2352; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=0U2zo71EC9Wu15E32rrl4zFFUOLw4/kKO/mst7UPUWU=; b=2GbmJS3Vbju9NJboam+oOXs/rlAtA5JKYqDguBg2nVmglA4UFZSDqROLiPMro4A+yLc4E6GJd L+ZMKz8GYknAHOi/NmKr4dQkGz7c3k1vqzpOectREg6I/R35utxE4Yj X-Developer-Key: i=peng.fan@nxp.com; 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Config SDHC1 clock 400MHz to support eMMC HS400ES mode 2. The original usdhc2 and usdhc3 root clock is 200MHz. Then WIFI on usdhc3 at SDR104 mode can work under 200MHz. But if imx93 work under Low Drive mode, the usdhc3 pad signal is not good under 200MHz, SDR104 mode can't work stable. Need to downgrade to 133MHz to let WIFI work stable. To cover all the cases, for Norminal Drive mode, keep usdhc root at 400MHz, then card(SD/wifi) can work at SDR104 mode under 200MHz to get the best performance. For Low Drive mode, bootloader need override usdhc root clock to 266MHz, and the card(SD/wifi) work at SDR104 mode under 133MHz, can work stable. Reviewed-by: Sherry Sun Signed-off-by: Haibo Chen Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx93.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index d762d96afcd5..9a7cb59e2c7f 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1018,6 +1018,9 @@ usdhc1: mmc@42850000 { <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC1_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; @@ -1032,6 +1035,9 @@ usdhc2: mmc@42860000 { <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC2_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; @@ -1095,6 +1101,9 @@ usdhc3: mmc@428b0000 { <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC3_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>;