| Message ID | 20240504-imx-clk-v1-10-f7915489d58d@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: imx: misc update/fix | expand |
Hello Peng, On Sat, May 04, 2024 at 08:49:03AM +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > For i.MX7D DRAM related mux clock, the clock source change should ONLY > be done done in low level asm code without accessing DRAM, and then > calling clk API to sync the HW clock status with clk tree, it should never > touch real clock source switch via clk API, so CLK_SET_PARENT_GATE flag > should NOT be added, otherwise, DRAM's clock parent will be disabled when > DRAM is active, and system will hang. From the description this is solving a system hang, but no fixes tag nor cc stable. Francesco
> Subject: Re: [PATCH 10/18] clk: imx: Remove CLK_SET_PARENT_GATE for > DRAM mux for i.MX7D > > Hello Peng, > > On Sat, May 04, 2024 at 08:49:03AM +0800, Peng Fan (OSS) wrote: > > From: Peng Fan <peng.fan@nxp.com> > > > > For i.MX7D DRAM related mux clock, the clock source change should ONLY > > be done done in low level asm code without accessing DRAM, and then > > calling clk API to sync the HW clock status with clk tree, it should > > never touch real clock source switch via clk API, so > > CLK_SET_PARENT_GATE flag should NOT be added, otherwise, DRAM's clock > > parent will be disabled when DRAM is active, and system will hang. > > From the description this is solving a system hang, but no fixes tag nor cc > stable. Not add fixes tab, because current upstream kernel not support DRAM freq update for 7D, so the issue will not happen in upstream kernel. But in case in future DRAM freq change needs change.. > > Francesco
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 2b77d1fc7bb9..1e1296e74835 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -498,9 +498,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel), CLK_SET_PARENT_GATE); hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel), CLK_SET_PARENT_GATE); hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel), CLK_SET_PARENT_GATE); - hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel), CLK_SET_PARENT_GATE); - hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2_flags("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel), CLK_SET_PARENT_GATE); hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE); hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE);