| Message ID | 20240724132415.1700386-1-andrei.stefanescu@oss.nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: s32g: add the pinctrl node | expand |
On 24/07/2024 15:24, Andrei Stefanescu wrote: > Add the pinctrl node in the device tree in order to enable the > S32G2/S32G3 pinctrl driver to probe. > > Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > V2 -> V1: moved the pinctrl node before the uart1 one to sort based > on the reg value, removed the status property, renamed the > jtag_pins node and jtag_grp* subnodes > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 50 +++++++++++++++++++++++ > arch/arm64/boot/dts/freescale/s32g3.dtsi | 52 +++++++++++++++++++++++- > 2 files changed, 101 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index fc19ae2e8d3b..fa054bfe7d5c 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -114,6 +114,56 @@ soc@0 { > #size-cells = <1>; > ranges = <0 0 0 0x80000000>; > > + pinctrl: pinctrl@4009c240 { > + compatible = "nxp,s32g2-siul2-pinctrl"; > + /* MSCR0-MSCR101 registers on siul2_0 */ > + reg = <0x4009c240 0x198>, > + /* MSCR112-MSCR122 registers on siul2_1 */ > + <0x44010400 0x2c>, > + /* MSCR144-MSCR190 registers on siul2_1 */ > + <0x44010480 0xbc>, > + /* IMCR0-IMCR83 registers on siul2_0 */ > + <0x4009ca40 0x150>, > + /* IMCR119-IMCR397 registers on siul2_1 */ > + <0x44010c1c 0x45c>, > + /* IMCR430-IMCR495 registers on siul2_1 */ > + <0x440110f8 0x108>; > + > + jtag_pins: jtag-pins { > + jtag-grp0 { > + pinmux = <0x0>; > + input-enable; > + bias-pull-up; > + slew-rate = <166>; > + }; > + > + jtag-grp1 { > + pinmux = <0x11>; > + slew-rate = <166>; > + }; > + > + jtag-grp2 { > + pinmux = <0x40>; > + input-enable; > + bias-pull-down; > + slew-rate = <166>; > + }; > + > + jtag-grp3 { > + pinmux = <0x23c0>, > + <0x23d0>, > + <0x2320>; > + }; > + > + jtag-grp4 { > + pinmux = <0x51>; > + input-enable; > + bias-pull-up; > + slew-rate = <166>; > + }; > + }; > + }; > + > uart0: serial@401c8000 { > compatible = "nxp,s32g2-linflexuart", > "fsl,s32v234-linflexuart"; > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > index c1b08992754b..b4226a9143c8 100644 > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > /* > - * Copyright 2021-2023 NXP > + * Copyright 2021-2024 NXP > * > * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> > * Ciprian Costea <ciprianmarian.costea@nxp.com> > @@ -171,6 +171,56 @@ soc@0 { > #size-cells = <1>; > ranges = <0 0 0 0x80000000>; > > + pinctrl: pinctrl@4009c240 { > + compatible = "nxp,s32g2-siul2-pinctrl"; > + /* MSCR0-MSCR101 registers on siul2_0 */ > + reg = <0x4009c240 0x198>, > + /* MSCR112-MSCR122 registers on siul2_1 */ > + <0x44010400 0x2c>, > + /* MSCR144-MSCR190 registers on siul2_1 */ > + <0x44010480 0xbc>, > + /* IMCR0-IMCR83 registers on siul2_0 */ > + <0x4009ca40 0x150>, > + /* IMCR119-IMCR397 registers on siul2_1 */ > + <0x44010c1c 0x45c>, > + /* IMCR430-IMCR495 registers on siul2_1 */ > + <0x440110f8 0x108>; > + > + jtag_pins: jtag-pins { > + jtag-grp0 { > + pinmux = <0x0>; > + input-enable; > + bias-pull-up; > + slew-rate = <166>; > + }; > + > + jtag-grp1 { > + pinmux = <0x11>; > + slew-rate = <166>; > + }; > + > + jtag-grp2 { > + pinmux = <0x40>; > + input-enable; > + bias-pull-down; > + slew-rate = <166>; > + }; > + > + jtag-grp3 { > + pinmux = <0x23c0>, > + <0x23d0>, > + <0x2320>; > + }; > + > + jtag-grp4 { > + pinmux = <0x51>; > + input-enable; > + bias-pull-up; > + slew-rate = <166>; > + }; > + }; > + }; > + > uart0: serial@401c8000 { > compatible = "nxp,s32g3-linflexuart", > "fsl,s32v234-linflexuart";
On Wed, Jul 24, 2024 at 04:24:15PM +0300, Andrei Stefanescu wrote: > Add the pinctrl node in the device tree in order to enable the > S32G2/S32G3 pinctrl driver to probe. > > Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index fc19ae2e8d3b..fa054bfe7d5c 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -114,6 +114,56 @@ soc@0 { #size-cells = <1>; ranges = <0 0 0 0x80000000>; + pinctrl: pinctrl@4009c240 { + compatible = "nxp,s32g2-siul2-pinctrl"; + /* MSCR0-MSCR101 registers on siul2_0 */ + reg = <0x4009c240 0x198>, + /* MSCR112-MSCR122 registers on siul2_1 */ + <0x44010400 0x2c>, + /* MSCR144-MSCR190 registers on siul2_1 */ + <0x44010480 0xbc>, + /* IMCR0-IMCR83 registers on siul2_0 */ + <0x4009ca40 0x150>, + /* IMCR119-IMCR397 registers on siul2_1 */ + <0x44010c1c 0x45c>, + /* IMCR430-IMCR495 registers on siul2_1 */ + <0x440110f8 0x108>; + + jtag_pins: jtag-pins { + jtag-grp0 { + pinmux = <0x0>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + + jtag-grp1 { + pinmux = <0x11>; + slew-rate = <166>; + }; + + jtag-grp2 { + pinmux = <0x40>; + input-enable; + bias-pull-down; + slew-rate = <166>; + }; + + jtag-grp3 { + pinmux = <0x23c0>, + <0x23d0>, + <0x2320>; + }; + + jtag-grp4 { + pinmux = <0x51>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + }; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index c1b08992754b..b4226a9143c8 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2023 NXP + * Copyright 2021-2024 NXP * * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> * Ciprian Costea <ciprianmarian.costea@nxp.com> @@ -171,6 +171,56 @@ soc@0 { #size-cells = <1>; ranges = <0 0 0 0x80000000>; + pinctrl: pinctrl@4009c240 { + compatible = "nxp,s32g2-siul2-pinctrl"; + /* MSCR0-MSCR101 registers on siul2_0 */ + reg = <0x4009c240 0x198>, + /* MSCR112-MSCR122 registers on siul2_1 */ + <0x44010400 0x2c>, + /* MSCR144-MSCR190 registers on siul2_1 */ + <0x44010480 0xbc>, + /* IMCR0-IMCR83 registers on siul2_0 */ + <0x4009ca40 0x150>, + /* IMCR119-IMCR397 registers on siul2_1 */ + <0x44010c1c 0x45c>, + /* IMCR430-IMCR495 registers on siul2_1 */ + <0x440110f8 0x108>; + + jtag_pins: jtag-pins { + jtag-grp0 { + pinmux = <0x0>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + + jtag-grp1 { + pinmux = <0x11>; + slew-rate = <166>; + }; + + jtag-grp2 { + pinmux = <0x40>; + input-enable; + bias-pull-down; + slew-rate = <166>; + }; + + jtag-grp3 { + pinmux = <0x23c0>, + <0x23d0>, + <0x2320>; + }; + + jtag-grp4 { + pinmux = <0x51>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + }; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart";
Add the pinctrl node in the device tree in order to enable the S32G2/S32G3 pinctrl driver to probe. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> --- V2 -> V1: moved the pinctrl node before the uart1 one to sort based on the reg value, removed the status property, renamed the jtag_pins node and jtag_grp* subnodes arch/arm64/boot/dts/freescale/s32g2.dtsi | 50 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 52 +++++++++++++++++++++++- 2 files changed, 101 insertions(+), 1 deletion(-)