| Message ID | 20240725094457.37739-4-y.varakala@phytec.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: freescale: imx8mp-phycore: Add devicetree overlays | expand |
On 25/07/2024 11:44, Yashwanth Varakala wrote: > Adds a devicetree containing reserved memory regions used for intercore > communication between A53 and M7 cores. > > Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de> > --- > arch/arm64/boot/dts/freescale/Makefile | 2 + > .../dts/freescale/imx8mp-phycore-rpmsg.dtso | 57 +++++++++++++++++++ > 2 files changed, 59 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index dedea4b5c319..80cc87d50301 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -177,9 +177,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb > imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo > imx8mp-phyboard-pollux-rdk-no-rtc-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-rtc.dtbo > imx8mp-phyboard-pollux-rdk-no-spiflash-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-spiflash.dtbo > +imx8mp-phyboard-pollux-rdk-rpmsg-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-rpmsg.dtbo > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-rtc.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-spiflash.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-rpmsg.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso > new file mode 100644 > index 000000000000..a5694f3aecaa > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso > @@ -0,0 +1,57 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2024 PHYTEC Messtechnik GmbH > + * Author: Dominik Haller <d.haller@phytec.de> > + * Cem Tenruh <c.tenruh@phytec.de> > + */ > + > +/dts-v1/; > +/plugin/; > + > +#include <dt-bindings/clock/imx8mp-clock.h> > + > +&{/} { > + imx8mp-cm7 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "fsl,imx8mn-cm7"; > + clocks = <&clk IMX8MP_CLK_M7_DIV>; > + mboxes = <&mu 0 1 > + &mu 1 1 > + &mu 3 1>; That's one or there entries? look wrong. > + mbox-names = "tx", "rx", "rxdb"; > + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; > + rsc-da = <0x55000000>; > + status = "okay"; Why? Did you disable it anywhere? You add a new node. > + }; > + > + reserved-memory { > + ranges; > + #address-cells = <2>; > + #size-cells = <2>; > + > + m7_reserved: m7@0x80000000 { > + no-map; > + reg = <0 0x80000000 0 0x1000000>; > + }; > + > + rsc_table: rsc_table@550ff000 { Please follow DTS coding style... This applies to all your contributions. Best regards, Krzysztof
> Subject: [PATCH 3/3] arm64: dts: Add phyBOARD-Pollux dts for rpmsg > > Adds a devicetree containing reserved memory regions used for > intercore communication between A53 and M7 cores. > > Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de> > --- > arch/arm64/boot/dts/freescale/Makefile | 2 + > .../dts/freescale/imx8mp-phycore-rpmsg.dtso | 57 > +++++++++++++++++++ > 2 files changed, 59 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp- > phycore-rpmsg.dtso > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > b/arch/arm64/boot/dts/freescale/Makefile > index dedea4b5c319..80cc87d50301 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -177,9 +177,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp- > phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs += > imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo > imx8mp-phyboard-pollux-rdk-no-rtc-dtbs += imx8mp-phyboard-pollux- > rdk.dtb imx8mp-phycore-no-rtc.dtbo imx8mp-phyboard-pollux-rdk-no- > spiflash-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no- > spiflash.dtbo > +imx8mp-phyboard-pollux-rdk-rpmsg-dtbs += imx8mp-phyboard- > pollux-rdk.dtb > +imx8mp-phycore-rpmsg.dtbo > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no- > eth.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-rtc.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no- > spiflash.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk- > rpmsg.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore- > rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phycore- > rpmsg.dtso > new file mode 100644 > index 000000000000..a5694f3aecaa > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso > @@ -0,0 +1,57 @@ > +// SPDX-License-Identifier: GPL-2.0 Dual license is better device tree. > +/* > + * Copyright (C) 2024 PHYTEC Messtechnik GmbH > + * Author: Dominik Haller <d.haller@phytec.de> > + * Cem Tenruh <c.tenruh@phytec.de> > + */ > + > +/dts-v1/; > +/plugin/; > + > +#include <dt-bindings/clock/imx8mp-clock.h> > + > +&{/} { > + imx8mp-cm7 { > + compatible = "fsl,imx8mn-cm7"; > + clocks = <&clk IMX8MP_CLK_M7_DIV>; > + mboxes = <&mu 0 1 > + &mu 1 1 > + &mu 3 1>; mboxes = <&mu1 0 1>, <&mu1 1 1>, <&mu1 3 1>; > + mbox-names = "tx", "rx", "rxdb"; > + memory-region = <&vdevbuffer>, <&vdev0vring0>, > <&vdev0vring1>, <&rsc_table>; > + rsc-da = <0x55000000>; Drop this "rsc-da". > + status = "okay"; Drop it, default is "okay". > + }; > + > + reserved-memory { > + ranges; > + #address-cells = <2>; > + #size-cells = <2>; > + > + m7_reserved: m7@0x80000000 { > + no-map; > + reg = <0 0x80000000 0 0x1000000>; > + }; > + > + rsc_table: rsc_table@550ff000 { "rsc-table@550ff000". Seems you not test this patch with linux remoteproc, otherwise you will see vring not set up. Regards, Peng.
Hello Peng, On Thu, 2024-08-01 at 02:27 +0000, Peng Fan wrote: > > Subject: [PATCH 3/3] arm64: dts: Add phyBOARD-Pollux dts for rpmsg > > > > Adds a devicetree containing reserved memory regions used for > > intercore communication between A53 and M7 cores. > > > > Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de> > > --- > > arch/arm64/boot/dts/freescale/Makefile | 2 + > > .../dts/freescale/imx8mp-phycore-rpmsg.dtso | 57 > > +++++++++++++++++++ > > 2 files changed, 59 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp- > > phycore-rpmsg.dtso > > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > > b/arch/arm64/boot/dts/freescale/Makefile > > index dedea4b5c319..80cc87d50301 100644 > > --- a/arch/arm64/boot/dts/freescale/Makefile > > +++ b/arch/arm64/boot/dts/freescale/Makefile > > @@ -177,9 +177,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp- > > phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs += > > imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo > > imx8mp-phyboard-pollux-rdk-no-rtc-dtbs += imx8mp-phyboard-pollux- > > rdk.dtb imx8mp-phycore-no-rtc.dtbo imx8mp-phyboard-pollux-rdk-no- > > spiflash-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no- > > spiflash.dtbo > > +imx8mp-phyboard-pollux-rdk-rpmsg-dtbs += imx8mp-phyboard- > > pollux-rdk.dtb > > +imx8mp-phycore-rpmsg.dtbo > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no- > > eth.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-rtc.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no- > > spiflash.dtb > > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk- > > rpmsg.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore- > > rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phycore- > > rpmsg.dtso > > new file mode 100644 > > index 000000000000..a5694f3aecaa > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso > > @@ -0,0 +1,57 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > Dual license is better device tree. > > > +/* > > + * Copyright (C) 2024 PHYTEC Messtechnik GmbH > > + * Author: Dominik Haller <d.haller@phytec.de> > > + * Cem Tenruh <c.tenruh@phytec.de> > > + */ > > + > > +/dts-v1/; > > +/plugin/; > > + > > +#include <dt-bindings/clock/imx8mp-clock.h> > > + > > +&{/} { > > + imx8mp-cm7 { > > + compatible = "fsl,imx8mn-cm7"; > > + clocks = <&clk IMX8MP_CLK_M7_DIV>; > > + mboxes = <&mu 0 1 > > + &mu 1 1 > > + &mu 3 1>; > > mboxes = <&mu1 0 > 1>, > > <&mu1 1 > 1>, > > <&mu1 3 1>; Thank you for the feedback. I checked and found only mu and mu2 labels of mailboxes are present. mu1 is not used in imx8mp.dtsi. Can you please tell me why I have to use mu1 here? > > > + mbox-names = "tx", "rx", "rxdb"; > > + memory-region = <&vdevbuffer>, <&vdev0vring0>, > > <&vdev0vring1>, <&rsc_table>; > > + rsc-da = <0x55000000>; > > Drop this "rsc-da". > > > + status = "okay"; > > Drop it, default is "okay". > > > + }; > > + > > + reserved-memory { > > + ranges; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + m7_reserved: m7@0x80000000 { > > + no-map; > > + reg = <0 0x80000000 0 0x1000000>; > > + }; > > + > > + rsc_table: rsc_table@550ff000 { > > "rsc-table@550ff000". Seems you not test this patch with linux > remoteproc, otherwise you will see vring not set up. > > Regards, > Peng.
> Subject: Re: [PATCH 3/3] arm64: dts: Add phyBOARD-Pollux dts for > rpmsg > > Hello Peng, > > On Thu, 2024-08-01 at 02:27 +0000, Peng Fan wrote: > > > Subject: [PATCH 3/3] arm64: dts: Add phyBOARD-Pollux dts for > rpmsg > > > > > > Adds a devicetree containing reserved memory regions used for > > > intercore communication between A53 and M7 cores. > > > > > > Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de> > > > --- > > > arch/arm64/boot/dts/freescale/Makefile | 2 + > > > .../dts/freescale/imx8mp-phycore-rpmsg.dtso | 57 > > > +++++++++++++++++++ > > > 2 files changed, 59 insertions(+) > > > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp- > > > phycore-rpmsg.dtso > > > > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > > > b/arch/arm64/boot/dts/freescale/Makefile > > > index dedea4b5c319..80cc87d50301 100644 > > > --- a/arch/arm64/boot/dts/freescale/Makefile > > > +++ b/arch/arm64/boot/dts/freescale/Makefile > > > @@ -177,9 +177,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp- > > > phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs > += > > > imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo > > > imx8mp-phyboard-pollux-rdk-no-rtc-dtbs += imx8mp-phyboard- > pollux- > > > rdk.dtb imx8mp-phycore-no-rtc.dtbo imx8mp-phyboard-pollux- > rdk-no- > > > spiflash-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore- > no- > > > spiflash.dtbo > > > +imx8mp-phyboard-pollux-rdk-rpmsg-dtbs += imx8mp-phyboard- > > > pollux-rdk.dtb > > > +imx8mp-phycore-rpmsg.dtbo > > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no- > eth.dtb > > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no- > rtc.dtb > > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no- > > > spiflash.dtb > > > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk- > > > rpmsg.dtb > > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb > > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb > > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait- > 1cp1.dtb > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore- > > > rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phycore- > > > rpmsg.dtso > > > new file mode 100644 > > > index 000000000000..a5694f3aecaa > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso > > > @@ -0,0 +1,57 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > > Dual license is better device tree. > > > > > +/* > > > + * Copyright (C) 2024 PHYTEC Messtechnik GmbH > > > + * Author: Dominik Haller <d.haller@phytec.de> > > > + * Cem Tenruh <c.tenruh@phytec.de> */ > > > + > > > +/dts-v1/; > > > +/plugin/; > > > + > > > +#include <dt-bindings/clock/imx8mp-clock.h> > > > + > > > +&{/} { > > > + imx8mp-cm7 { > > > + compatible = "fsl,imx8mn-cm7"; > > > + clocks = <&clk IMX8MP_CLK_M7_DIV>; > > > + mboxes = <&mu 0 1 > > > + &mu 1 1 > > > + &mu 3 1>; > > > > mboxes = <&mu1 0 > > 1>, > > > > <&mu1 1 > > 1>, > > > > <&mu1 3 1>; > Thank you for the feedback. I checked and found only mu and mu2 > labels of mailboxes are present. mu1 is not used in imx8mp.dtsi. Can > you please tell me why I have to use mu1 here? I just copy and paste what imx8mp-evk use to here. You need update according to your usage. Regards, Peng.
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index dedea4b5c319..80cc87d50301 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -177,9 +177,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo imx8mp-phyboard-pollux-rdk-no-rtc-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-rtc.dtbo imx8mp-phyboard-pollux-rdk-no-spiflash-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-spiflash.dtbo +imx8mp-phyboard-pollux-rdk-rpmsg-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-rpmsg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-rtc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-spiflash.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso new file mode 100644 index 000000000000..a5694f3aecaa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Dominik Haller <d.haller@phytec.de> + * Cem Tenruh <c.tenruh@phytec.de> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/imx8mp-clock.h> + +&{/} { + imx8mp-cm7 { + compatible = "fsl,imx8mn-cm7"; + clocks = <&clk IMX8MP_CLK_M7_DIV>; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + rsc-da = <0x55000000>; + status = "okay"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + m7_reserved: m7@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + rsc_table: rsc_table@550ff000 { + no-map; + reg = <0 0x550ff000 0 0x1000>; + }; + + vdevbuffer: vdevbuffer@55400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x55400000 0 0x100000>; + }; + + vdev0vring0: vdev0vring0@55000000 { + no-map; + reg = <0 0x55000000 0 0x8000>; + }; + + vdev0vring1: vdev0vring1@55008000 { + no-map; + reg = <0 0x55008000 0 0x8000>; + }; + }; +};
Adds a devicetree containing reserved memory regions used for intercore communication between A53 and M7 cores. Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de> --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx8mp-phycore-rpmsg.dtso | 57 +++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso