diff mbox series

arm64: dts: imx93: add cache info

Message ID 20240801081111.1492688-1-peng.fan@oss.nxp.com (mailing list archive)
State New
Headers show
Series arm64: dts: imx93: add cache info | expand

Commit Message

Peng Fan (OSS) Aug. 1, 2024, 8:11 a.m. UTC 
From: Peng Fan <peng.fan@nxp.com>

i.MX93 features two Cortex-A55 cores with per core L1 Instruction
cache size 32KB, L1 data cache size 32KB, per core L2 cache 64KB, and
unified 256KB L3 cache.

Add the cache info to remove cacheinfo warnings at boot:
"cacheinfo: Unable to detect cache hierarchy for CPU 0"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 42 ++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

Comments

Stefan Wahren Aug. 2, 2024, 7:25 p.m. UTC | #1 
Am 01.08.24 um 10:11 schrieb Peng Fan (OSS):
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX93 features two Cortex-A55 cores with per core L1 Instruction
> cache size 32KB, L1 data cache size 32KB, per core L2 cache 64KB, and
> unified 256KB L3 cache.
>
> Add the cache info to remove cacheinfo warnings at boot:
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>

Reviewed-by: Stefan Wahren <wahrenst@gmx.net>

Thanks
Shawn Guo Aug. 13, 2024, 3:21 a.m. UTC | #2 
On Thu, Aug 01, 2024 at 04:11:11PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> i.MX93 features two Cortex-A55 cores with per core L1 Instruction
> cache size 32KB, L1 data cache size 32KB, per core L2 cache 64KB, and
> unified 256KB L3 cache.
> 
> Add the cache info to remove cacheinfo warnings at boot:
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index 4a3f42355cb8..8f17b1fbfba0 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -69,6 +69,13 @@  A55_0: cpu@0 {
 			enable-method = "psci";
 			#cooling-cells = <2>;
 			cpu-idle-states = <&cpu_pd_wait>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_cache_l0>;
 		};
 
 		A55_1: cpu@100 {
@@ -78,8 +85,43 @@  A55_1: cpu@100 {
 			enable-method = "psci";
 			#cooling-cells = <2>;
 			cpu-idle-states = <&cpu_pd_wait>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_cache_l1>;
 		};
 
+		l2_cache_l0: l2-cache-l0 {
+			compatible = "cache";
+			cache-size = <65536>;
+			cache-line-size = <64>;
+			cache-sets = <256>;
+			cache-level = <2>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l2_cache_l1: l2-cache-l1 {
+			compatible = "cache";
+			cache-size = <65536>;
+			cache-line-size = <64>;
+			cache-sets = <256>;
+			cache-level = <2>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l3_cache: l3-cache {
+			compatible = "cache";
+			cache-size = <262144>;
+			cache-line-size = <64>;
+			cache-sets = <256>;
+			cache-level = <3>;
+			cache-unified;
+		};
 	};
 
 	osc_32k: clock-osc-32k {