[v2,3/3] arm64: dts: Add phyBOARD-Pollux dtso for rpmsg

Commit Message

Yashwanth Varakala Aug. 20, 2024, 5:18 p.m. UTC

Adds a devicetree containing reserved memory regions used for intercore
communication between A53 and M7 cores.

Signed-off-by: Yashwanth Varakala <[e-mail]>
---
Changes in v2:
- Updated license.
- Updated devicetree properties.
- Replaced imx8mp-cm7 with core-m7 node name.
- Updated reserved-memory node unit addresses in ascending order.

 arch/arm64/boot/dts/freescale/Makefile        |  2 +
 .../dts/freescale/imx8mp-phycore-rpmsg.dtso   | 55 +++++++++++++++++++
 2 files changed, 57 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso

Comments

Shawn Guo Sept. 1, 2024, 7:30 a.m. UTC | #1

On Tue, Aug 20, 2024 at 07:18:48PM +0200, Yashwanth Varakala wrote:
> Adds a devicetree containing reserved memory regions used for intercore
> communication between A53 and M7 cores.
> 
> Signed-off-by: Yashwanth Varakala <[e-mail]>

I'm getting these warnings.

arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso:25.3-10: Warning (ranges_format): /fragment@0/__overlay__/reserved-memory:ranges: empty "ranges" property but its #size-cells (2) differs from /fragment@0/__overlay__ (1)
arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso:24.18-54.4: Warning (avoid_default_addr_size): /fragment@0/__overlay__/reserved-memory: Relying on default #address-cells value
arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso:24.18-54.4: Warning (avoid_default_addr_size): /fragment@0/__overlay__/reserved-memory: Relying on default #size-cells value

Shawn

Patch

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index dedea4b5c319..80cc87d50301 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -177,9 +177,11 @@  dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
 imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo
 imx8mp-phyboard-pollux-rdk-no-rtc-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-rtc.dtbo
 imx8mp-phyboard-pollux-rdk-no-spiflash-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-spiflash.dtbo
+imx8mp-phyboard-pollux-rdk-rpmsg-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-rpmsg.dtbo
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-rtc.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-spiflash.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-rpmsg.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso
new file mode 100644
index 000000000000..f9fba558dcb0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-rpmsg.dtso
@@ -0,0 +1,55 @@ 
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Dominik Haller <[e-mail]>
+ * 	   Cem Tenruh <[e-mail]>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+&{/} {
+	core-m7 {
+		compatible = "fsl,imx8mn-cm7";
+		clocks = <&clk IMX8MP_CLK_M7_DIV>;
+		mboxes = <&mu 0 1>,
+			<&mu 1 1>,
+			<&mu 3 1>;
+		mbox-names = "tx", "rx", "rxdb";
+		memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		vdev0vring0: vdev0vring0@55000000 {
+			no-map;
+			reg = <0 0x55000000 0 0x8000>;
+		};
+
+		vdev0vring1: vdev0vring1@55008000 {
+			no-map;
+			reg = <0 0x55008000 0 0x8000>;
+		};
+
+		rsc_table: rsc-table@550ff000 {
+			no-map;
+			reg = <0 0x550ff000 0 0x1000>;
+		};
+
+		vdevbuffer: vdevbuffer@55400000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0 0x55400000 0 0x100000>;
+		};
+
+		m7_reserved: m7@80000000 {
+			no-map;
+			reg = <0 0x80000000 0 0x1000000>;
+		};
+	};
+};