| Message ID | 20240905183228.517422-1-tharvey@gateworks.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration | expand |
On Thu, Sep 05, 2024 at 11:32:28AM -0700, Tim Harvey wrote: > The GW74xx D revision has added a M2SKT_GPIO10 GPIO which routes to the > GPIO10 pin of the M.2 socket for compatibility with certain devices. > > Add the iomux and a line name for this. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index d765b7972841..9885948952b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -299,7 +299,7 @@ &gpio2 { &gpio3 { gpio-line-names = "", "", "", "", "", "", "m2_rst", "", - "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "m2_gpio10", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -816,6 +816,7 @@ MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
The GW74xx D revision has added a M2SKT_GPIO10 GPIO which routes to the GPIO10 pin of the M.2 socket for compatibility with certain devices. Add the iomux and a line name for this. Signed-off-by: Tim Harvey <tharvey@gateworks.com> --- arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)