| Message ID | 20240930132344.3001876-4-andrei.stefanescu@oss.nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | pinctrl: s32: add missing pins and an S32G3 compatible | expand |
On 30/09/2024 15:23, Andrei Stefanescu wrote: > Add the newly introduced S32G3 compatible for the pinctrl node. > Currently, it will fall back to the S32G2 compatible. > > Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > arch/arm64/boot/dts/freescale/s32g3.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > index b4226a9143c8..f6aafe44c9d7 100644 > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi > @@ -172,7 +172,8 @@ soc@0 { > ranges = <0 0 0 0x80000000>; > > pinctrl: pinctrl@4009c240 { > - compatible = "nxp,s32g2-siul2-pinctrl"; > + compatible = "nxp,s32g3-siul2-pinctrl", > + "nxp,s32g2-siul2-pinctrl"; > /* MSCR0-MSCR101 registers on siul2_0 */ > reg = <0x4009c240 0x198>, > /* MSCR112-MSCR122 registers on siul2_1 */
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index b4226a9143c8..f6aafe44c9d7 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -172,7 +172,8 @@ soc@0 { ranges = <0 0 0 0x80000000>; pinctrl: pinctrl@4009c240 { - compatible = "nxp,s32g2-siul2-pinctrl"; + compatible = "nxp,s32g3-siul2-pinctrl", + "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ reg = <0x4009c240 0x198>, /* MSCR112-MSCR122 registers on siul2_1 */
Add the newly introduced S32G3 compatible for the pinctrl node. Currently, it will fall back to the S32G2 compatible. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)