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b=BgeSXHuwEi9ZZr63ZyrgUERXHVIFoD+OSWc0llxLnMPtgMSMYIJht6GV2CnzNd3x5La94bLdqMWZVlwszon48PjCn9XJdk/oTCy6dBf4xTKEhV7ZKJtV+H/5sr1aenBgk6Vv6rLXrs8mnPv6F7ic5XZNRewDbdTt0WHIZxY7ORICbbzHK0EdXpbqJExZ4FygZciI7YoVgcwV53iS0GhNmkz5LpL4quQc1NyJxmo92Xvhrl0r91AeUXaE9qsEeitHrHnMjwVp5VPdor0x6OIIGdUcz0GImzq+XoVysdkaup5BpQqfKtsCtL+bl18ezH/wBLXw8X+V2MVscj0MT4ZEWQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB8510.eurprd04.prod.outlook.com (2603:10a6:102:211::7) by PA1PR04MB10178.eurprd04.prod.outlook.com (2603:10a6:102:463::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.28; Tue, 22 Oct 2024 06:08:36 +0000 Received: from PAXPR04MB8510.eurprd04.prod.outlook.com ([fe80::a7c2:e2fa:8e04:40db]) by PAXPR04MB8510.eurprd04.prod.outlook.com ([fe80::a7c2:e2fa:8e04:40db%7]) with mapi id 15.20.8069.027; Tue, 22 Oct 2024 06:08:36 +0000 From: Wei Fang To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vladimir.oltean@nxp.com, claudiu.manoil@nxp.com, xiaoning.wang@nxp.com, Frank.Li@nxp.com, christophe.leroy@csgroup.eu, linux@armlinux.org.uk, bhelgaas@google.com, horms@kernel.org Cc: imx@lists.linux.dev, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, alexander.stein@ew.tq-group.com Subject: [PATCH v4 net-next 11/13] net: enetc: optimize the allocation of tx_bdr Date: Tue, 22 Oct 2024 13:52:21 +0800 Message-Id: <20241022055223.382277-12-wei.fang@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022055223.382277-1-wei.fang@nxp.com> References: <20241022055223.382277-1-wei.fang@nxp.com> X-ClientProxiedBy: SG2PR02CA0044.apcprd02.prod.outlook.com (2603:1096:3:18::32) To PAXPR04MB8510.eurprd04.prod.outlook.com (2603:10a6:102:211::7) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB8510:EE_|PA1PR04MB10178:EE_ X-MS-Office365-Filtering-Correlation-Id: ea7e4a5e-0173-4ee2-22fc-08dcf25ff720 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|376014|7416014|1800799024|366016|921020|38350700014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RaNQ1M/11Z6+ehPmQYZQdzSdRacKY9dIc/oBhWCxo/n064oaShQrZwx7nUokP2e6qxogtt4j06nf2kO19z8OZ8XTDBivvknmAM7uVEG/gy/E8bl8dMAvnY9qqn1jUZe8sCFCQTM2jL8NMqDmXSucufqQ50TT1jwK+ihvDUZtwaFdRVI8lHNnFywcp8byLcF/PKWC+Zi8OwG140D1E6WboG/K2KLcAV/huhQbH45cuKMGEDvlAfO3qayW/pRWlfDcnVVy/HeX3dw0wQFQX0xjW7j7zdP4e/3DHTpw8SWkVzhIA1wPUBU+sOomPwJqNbrp+uRIL/FOAHJ4cce5xdL1Y0V9AR/jeOXDa0XecuoR6K/ZBOJeWlCG26vWFEgNafc2WssPlL8MvlMp88JnHJCfSqObFWAQ+38+kUnnBjkikB02SYjBsIUzMEkPrrfyxx9eIn6YHtCoPE/7faUye74ZfjsISb+HQ2MY1OB4XzdewaCXP068HQ2V2U9naXzLLPoK+QIjs3NjBy6Ya3rLfX3zcdBBgsHSngFx9vjckjsh5lJnLg1KRRvQIiFBeE+HTJkBFsON+q87HSpEZ3z5+VUrUmOxMelW6hycaxsWmPM83NDWCmiAmQ5IpHmR+u9DMYibxbUKqZostBW5AnTV51+sqf2Q8sPHUukwX858GEufGWvMVPnLLS1KyWfb7abtlYWeEXSacAbAjSbsCJgeJemBXjgOsMq6Szd7s6TCcBsPWnUSuvi355BUO56g44QPMZgic0r4KvfIjxrpgH6bpKCsEbbRc4nNvyaH4gPCjuRuxhuzvHvNpxDzfQrk8L9JciKP/UEdebt2aJl04jtyfxYpbxiVL67LW7QaeNF+CbBe0d+iBTyUPSutJXW1Halh2zxv7dryUmAigf/nK725+lUbgTk86Ltl0ceM29c7E/IKDptmKc69ySyWSZxiYP7R2RQ4oAbPf7nJvgAeSFCIkElHnnD+0hsd357tAnz5rdMKQOrd0R5bjtgZaX5Nv44eHeU+UJDdwnX6jqgMDEezuXHuUiNobmgocfRIlgH7h77JuBvXARJtONNfYfndaX0VwTlVMYMmFw0xP62ioekOWuQ/WCqUfY/U2Dg+ygWiF0cnFt6Jn2lC1srna+EGdgUZjX/8x351/9HTu9szLKb/Bp8NK69hNWzvCvfft4Bsyj6qsn/9C7RO9yFQ+8B3+aQ6doVbTsptZU2/vM0XHO/6biaZYnmxPL7s11VaTewJPWGc3Iy38LERzM+XCgdpoBCXc7WLov2Ox6A/b1tMKvSW9mMCFo6KdFx0WlGaqkIysgAyUCocBXvjcJp2ZhukAFCEihm7O9cqA3GjPIZNEfpuVskbdo6Nntr7Bb5ixub3Ce2i/OIRBPJEdVFIrtsYe068xWeUPyfJ8i6Vx9EpIWsBbpZlnHm0Nix4YxtawXn7T2WdWBuQFeardRic2+NNAsW97kFXnyXxWmu5HVV5HPeYfOT65KIqvNN1N2Zkcj6TLe0ohW++orTL1iivxRvMgZthFAIONseoQL/FX2ZMsBqVqDsQT2ZWWsxOXnpXWllkntiLl5PghoRbPDwIEUMGACzcK2+K X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ea7e4a5e-0173-4ee2-22fc-08dcf25ff720 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8510.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 06:08:36.3996 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BuC3jZH92avA1d2aq9JYFxtpvgdIFxvpHwQCphEeSQefidMdN5sXdojhpv5QOsYqEt781D49SmS7U+knPuhXug== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR04MB10178 From: Clark Wang There is a situation where num_tx_rings cannot be divided by bdr_int_num. For example, num_tx_rings is 8 and bdr_int_num is 3. According to the previous logic, this results in two tx_bdr corresponding memories not being allocated, so when sending packets to tx ring 6 or 7, wild pointers will be accessed. Of course, this issue doesn't exist on LS1028A, because its num_tx_rings is 8, and bdr_int_num is either 1 or 2. However, there is a risk for the upcoming i.MX95. Therefore, it is necessary to ensure that each tx_bdr can be allocated to the corresponding memory. Signed-off-by: Clark Wang Signed-off-by: Wei Fang Reviewed-by: Claudiu Manoil Reviewed-by: Frank Li --- v2 changes: This patch is separated from v1 patch 9 ("net: enetc: optimize the allocation of tx_bdr"). Only the optimized part is kept. v3: no changes, just rebase the patch from the previous one. v4: no changes --- drivers/net/ethernet/freescale/enetc/enetc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c index bd725561b8a2..bccbeb1f355c 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc.c +++ b/drivers/net/ethernet/freescale/enetc/enetc.c @@ -3049,10 +3049,10 @@ static void enetc_int_vector_destroy(struct enetc_ndev_priv *priv, int i) int enetc_alloc_msix(struct enetc_ndev_priv *priv) { struct pci_dev *pdev = priv->si->pdev; + int v_tx_rings, v_remainder; int num_stack_tx_queues; int first_xdp_tx_ring; int i, n, err, nvec; - int v_tx_rings; nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num; /* allocate MSIX for both messaging and Rx/Tx interrupts */ @@ -3066,9 +3066,12 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv) /* # of tx rings per int vector */ v_tx_rings = priv->num_tx_rings / priv->bdr_int_num; + v_remainder = priv->num_tx_rings % priv->bdr_int_num; for (i = 0; i < priv->bdr_int_num; i++) { - err = enetc_int_vector_init(priv, i, v_tx_rings); + int num_tx_rings = i < v_remainder ? v_tx_rings + 1 : v_tx_rings; + + err = enetc_int_vector_init(priv, i, num_tx_rings); if (err) goto fail; }