diff mbox series

[1/3] arm64: dts: imx8qxp-mek: replace hardcode 0 with IMX_LPCG_CLK_0

Message ID 20241025220810.1833819-1-Frank.Li@nxp.com (mailing list archive)
State In Next, archived
Headers show
Series [1/3] arm64: dts: imx8qxp-mek: replace hardcode 0 with IMX_LPCG_CLK_0 | expand

Commit Message

Frank Li Oct. 25, 2024, 10:08 p.m. UTC 
Update clock settings to use the macro IMX_LPCG_CLK_0 instead of the
hardcoded value 0. The first argument of lpcg is indices, not index.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Shawn Guo Nov. 2, 2024, 6:48 a.m. UTC | #1 
On Fri, Oct 25, 2024 at 06:08:08PM -0400, Frank Li wrote:
> Update clock settings to use the macro IMX_LPCG_CLK_0 instead of the
> hardcoded value 0. The first argument of lpcg is indices, not index.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>

Applied all, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 2afebe523fa9d..531236d83caa4 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -230,8 +230,8 @@  &esai0 {
 			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
 			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
 			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
-			<&esai0_lpcg 0>;
-	assigned-clock-parents = <&aud_pll_div0_lpcg 0>;
+			<&esai0_lpcg IMX_LPCG_CLK_0>;
+	assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>;
 	assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
 	pinctrl-0 = <&pinctrl_esai0>;
 	pinctrl-names = "default";
@@ -411,12 +411,12 @@  pca6416: gpio@20 {
 	cs42888: audio-codec@48 {
 		compatible = "cirrus,cs42888";
 		reg = <0x48>;
-		clocks = <&mclkout0_lpcg 0>;
+		clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "mclk";
 		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
 				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
 				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
-				<&mclkout0_lpcg 0>;
+				<&mclkout0_lpcg IMX_LPCG_CLK_0>;
 		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
 		reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>;
 		VA-supply = <&reg_audio>;