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b=jBZ2GizhmhkNjqtEFReazZesP38M4h5iGXSBpwnL3aoyQrBQHqM0pGZS2ScB5laIETlH/qNJwFzBaJAyMKEniXe+iYu5+tb999yaDM+oBK+B/xdbaKCUmkrBSDS9Dp5ChCgrbN1MoRu2+FAv1cyGNEvJ2KnrUklQtJH0k+nP9+G+FrAxmE/545QxWC2XaTcVT3IGeZu0JwuX+PVTv7T3RPgwysn5anv5DRbXjoDbg/jI3q1+g7A/07s2kYbybWpJR7RqLr0txmHI1dW0lrrNKcZ1WVzPx+HntGOu+hmv5zOOIx+295koVB3XkmMAaAhQxoymhhxFOGuo4JnozLJkTQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) by DB9PR04MB8139.eurprd04.prod.outlook.com (2603:10a6:10:248::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.20; Thu, 31 Oct 2024 07:57:41 +0000 Received: from AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93]) by AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93%6]) with mapi id 15.20.8114.015; Thu, 31 Oct 2024 07:57:41 +0000 From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, frank.li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, kernel@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Frank Li , Richard Zhu Subject: [PATCH v5 08/10] PCI: imx6: Use dwc common suspend resume method Date: Thu, 31 Oct 2024 16:06:53 +0800 Message-Id: <20241031080655.3879139-9-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241031080655.3879139-1-hongxing.zhu@nxp.com> References: <20241031080655.3879139-1-hongxing.zhu@nxp.com> X-ClientProxiedBy: SG2PR04CA0184.apcprd04.prod.outlook.com (2603:1096:4:14::22) To AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8676:EE_|DB9PR04MB8139:EE_ X-MS-Office365-Filtering-Correlation-Id: dcf341c7-0648-4fbb-e6c4-08dcf981b205 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|52116014|376014|1800799024|366016|921020|38350700014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fjRY7+qEKYHPtnsY9J4pqOG4OSpEl+0q5Ejrq1wLcfXFkj7ysqzrrXVjoIiz8+ePIMcF3s46dDBeOk0sNhoHgNhgJ2J1yhHRSCo0RKO7KYdOSEzh04CX+pvz24fOnzjd3W/ThCpZRLU3tmB/Z9evhdWtTnveJWjVrHFLkn3Xbu9WWEpLAh2WI9fOEzgsBENvGfiXjs5Fxr4zTNP6YiWGDYRnq3lRAKyz2k5iJkZ4wlNmQQuePNdE61l8HGxy8B22m0w3DJQD+QDuEmF/QeMLkl2WSUlPo2Cz3/mS9lNRXHVSdF/EyDo6CFeNvmiYrUG0348lY0w2rcKzxXDofmeAPKQIqY72zCyfBU79UnnW5fYX9RyCxoPZX72YPe/n5AToQDgkdclXB6G0K9+5PcqarueQmuL2rgEZLpQpmD7OBmvQrZ7opbyK7H+r6/5axrGMJ+Szbr5Z7dXDX96Xht9XzTdYNHe1SFNgWjpm8H+T0UzinoYFOZLOXckaDWCEwi8x7fFCUuORbfO7oZl1W3DYzRmdyFCWH5gi6RfLQkhdptok53Ogy+S9c+2sH0vQ+Kr03rjYhMd12Toc7aatyGrxPBSOsurJAOv52DEL2ryjK/Xv4MxjQmT8FatG5wRSbaL254G73Nq3ZQhZJMuEKafVrOWXLPXLHySeqdhKq6TZVpm7v78RxFNjqUr6Lr7NphhMuU6B06KksobaeN+yEcAtNW/HtRQs5m6ErBFh5DC78PljwNLOKsdDPYpB6HBjLt/3KAmtdU6gU3LMq31pZA88M58cWpiF1wzAVVzsI0yBlYKRrgPZx/N7wYaDilOXDvmQxR77pJv+Ap6shDJRCpegURtPLjYmpnTQL2Lvvfe8ktZWSUf3tnGTEbOLoczY+PUCIyVEDb33S8MK8i16IRm26vMJrKsZY6eNckwhCkar2lv1rgo2qFK5NTmnhdGX4433GxdEFHp4+B2Sorp8S/2OgRLcLZa3bnXaML6jhladDMq5vM2+l7T9QtvOQBJJPB4sb9qMPCJijlx1jdw1cl6Nfw+vCo/+6nQNGFKqgWsDcFrkpX08YbGFJYpOf4G6utgTMxj3rD+/HwCRBCs9GIRHZHgeJpZG+M/qVY+C1GCOLE94AhwH+XdMLJXkE9ep9skIsNQ4k4lal/yWNm5AT/p6YY1G7is2bScwsUlMhXxL2S04U+TxeZGmth5T7PPMbE/zgKQhK7cSMu1pB5HMqef8MnQFgNjbrxpDjsEvuI5s5UdvY79it6sRjpKvahcSHy0on1TWpdfGEDIB7KxlSQ4Hqg3nErkGi6t/MAD75Y+HUFxhxXUYNVTXih5oDSqcHjZJAO+aLeuKII/AeJQiTMj8lccpyRL3yioVkcWKqfuo3cqbZEkUAQEZCuC8lKRfT5ZNW+tJjX0HaHamwBtMPDCN9XVzEIzHEx0kUu2X4uSAVP6zLPNaLMHnca9IcX/lnMMAl1Bt6JweLyOdgoNrvUVJJm3V5zrnLev8Tam12w307fGRXwlvdcOv0pG7zbwaHzNTkbGrX+yFYPkFRbxmPeXl3qYVjlH+sYLt5yqTr0CfBTan91UPwpxlSGNBYU2iKdTG X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: dcf341c7-0648-4fbb-e6c4-08dcf981b205 X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8676.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2024 07:57:41.4990 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DtXLmAZzonssS/YwtKdLvTnNnY4TQ2ZdLIP+p2aWjyrIqzDgXl1uVJ+B4/7zjTgCHk9hxHEnbP+LQC7FAE4CVg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8139 From: Frank Li Call common dwc suspend/resume function. Use dwc common iATU method to send out PME_TURN_OFF message. In Old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD bit in iATU Ctrl2 register is reserved. So the generic DWC implementation of sending the PME_Turn_Off message using a dummy MMIO write cannot be used. Use previouse method to kick off PME_TURN_OFF MSG for these platforms. Replace the imx_pcie_stop_link() and imx_pcie_host_exit() by dw_pcie_suspend_noirq() in imx_pcie_suspend_noirq(). dw_pcie_suspend_noirq() dw_pcie_stop_link(); pci->pp.ops->deinit(); imx_pcie_host_exit(); Replace the imx_pcie_host_init(), dw_pcie_setup_rc() and imx_pcie_start_link() by dw_pcie_resume_noirq() in imx_pcie_resume_noirq(). dw_pcie_resume_noirq() pci->pp.ops->init(); imx_pcie_host_init(); dw_pcie_setup_rc(); dw_pcie_start_link(); imx_pcie_start_link(); Signed-off-by: Frank Li Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 96 ++++++++++----------------- 1 file changed, 35 insertions(+), 61 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index dbcf22e440e2..410a31e5f82a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -33,6 +33,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) @@ -83,6 +84,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) #define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) #define IMX_PCIE_FLAG_CLOCKS_OPTIONAL BIT(9) +#define IMX_PCIE_FLAG_CUSTOM_PME_TURNOFF BIT(10) #define imx_check_flag(pci, val) (pci->drvdata->flags & val) @@ -107,19 +109,18 @@ struct imx_pcie_drvdata { int (*init_phy)(struct imx_pcie *pcie); int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); int (*core_reset)(struct imx_pcie *pcie, bool assert); + const struct dw_pcie_host_ops *ops; }; struct imx_pcie { struct dw_pcie *pci; struct gpio_desc *reset_gpiod; - bool link_is_up; struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; struct reset_control *pciephy_reset; struct reset_control *apps_reset; - struct reset_control *turnoff_reset; u32 tx_deemph_gen1; u32 tx_deemph_gen2_3p5db; u32 tx_deemph_gen2_6db; @@ -898,13 +899,11 @@ static int imx_pcie_start_link(struct dw_pcie *pci) dev_info(dev, "Link: Only Gen1 is enabled\n"); } - imx_pcie->link_is_up = true; tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); return 0; err_reset_phy: - imx_pcie->link_is_up = false; dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); @@ -1023,9 +1022,32 @@ static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) return cpu_addr - entry->offset; } +/* + * In Old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD bit in iATU Ctrl2 + * register is reserved. So the generic DWC implementation of sending the + * PME_Turn_Off message using a dummy MMIO write cannot be used. + */ +static void imx_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); + + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); + + usleep_range(PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US); +} + + static const struct dw_pcie_host_ops imx_pcie_host_ops = { .init = imx_pcie_host_init, .deinit = imx_pcie_host_exit, + .pme_turn_off = imx_pcie_pme_turn_off, +}; + +static const struct dw_pcie_host_ops imx_pcie_host_dw_pme_ops = { + .init = imx_pcie_host_init, + .deinit = imx_pcie_host_exit, }; static const struct dw_pcie_ops dw_pcie_ops = { @@ -1146,43 +1168,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, return 0; } -static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie) -{ - struct device *dev = imx_pcie->pci->dev; - - /* Some variants have a turnoff reset in DT */ - if (imx_pcie->turnoff_reset) { - reset_control_assert(imx_pcie->turnoff_reset); - reset_control_deassert(imx_pcie->turnoff_reset); - goto pm_turnoff_sleep; - } - - /* Others poke directly at IOMUXC registers */ - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_PM_TURN_OFF, - IMX6SX_GPR12_PCIE_PM_TURN_OFF); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); - break; - default: - dev_err(dev, "PME_Turn_Off not implemented\n"); - return; - } - - /* - * Components with an upstream port must respond to - * PME_Turn_Off with PME_TO_Ack but we can't check. - * - * The standard recommends a 1-10ms timeout after which to - * proceed anyway as if acks were received. - */ -pm_turnoff_sleep: - usleep_range(1000, 10000); -} - static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) { u8 offset; @@ -1206,36 +1191,26 @@ static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) static int imx_pcie_suspend_noirq(struct device *dev) { struct imx_pcie *imx_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx_pcie->pci->pp; if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; imx_pcie_msi_save_restore(imx_pcie, true); - imx_pcie_pm_turnoff(imx_pcie); - imx_pcie_stop_link(imx_pcie->pci); - imx_pcie_host_exit(pp); - - return 0; + return dw_pcie_suspend_noirq(imx_pcie->pci); } static int imx_pcie_resume_noirq(struct device *dev) { int ret; struct imx_pcie *imx_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx_pcie->pci->pp; if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; - ret = imx_pcie_host_init(pp); + ret = dw_pcie_resume_noirq(imx_pcie->pci); if (ret) return ret; imx_pcie_msi_save_restore(imx_pcie, false); - dw_pcie_setup_rc(pp); - - if (imx_pcie->link_is_up) - imx_pcie_start_link(imx_pcie->pci); return 0; } @@ -1267,11 +1242,14 @@ static int imx_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &dw_pcie_ops; - pci->pp.ops = &imx_pcie_host_ops; imx_pcie->pci = pci; imx_pcie->drvdata = of_device_get_match_data(dev); + pci->pp.ops = &imx_pcie_host_dw_pme_ops; + if (imx_pcie->drvdata->ops) + pci->pp.ops = imx_pcie->drvdata->ops; + /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1345,13 +1323,6 @@ static int imx_pcie_probe(struct platform_device *pdev) break; } - /* Grab turnoff reset */ - imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); - if (IS_ERR(imx_pcie->turnoff_reset)) { - dev_err(dev, "Failed to get TURNOFF reset control\n"); - return PTR_ERR(imx_pcie->turnoff_reset); - } - if (imx_pcie->drvdata->gpr) { /* Grab GPR config register range */ imx_pcie->iomuxc_gpr = @@ -1430,6 +1401,7 @@ static int imx_pcie_probe(struct platform_device *pdev) if (ret < 0) return ret; } else { + pci->pp.use_atu_msg = true; ret = dw_pcie_host_init(&pci->pp); if (ret < 0) return ret; @@ -1494,6 +1466,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .init_phy = imx6sx_pcie_init_phy, .enable_ref_clk = imx6sx_pcie_enable_ref_clk, .core_reset = imx6sx_pcie_core_reset, + .ops = &imx_pcie_host_ops, }, [IMX6QP] = { .variant = IMX6QP, @@ -1511,6 +1484,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .init_phy = imx_pcie_init_phy, .enable_ref_clk = imx6q_pcie_enable_ref_clk, .core_reset = imx6qp_pcie_core_reset, + .ops = &imx_pcie_host_ops, }, [IMX7D] = { .variant = IMX7D,