From patchwork Tue Nov 19 15:00:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Petrous via B4 Relay X-Patchwork-Id: 13880053 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8C1B1CFEA1; Tue, 19 Nov 2024 15:01:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732028464; cv=none; b=rE1DqD3S1NvcTp1bmsS3bFPX2bDdC6KY5mFD6txX4cNMn7L8v80dls8c5in3inH55u+u22cp86PX6vISFdIOMi9Bw/QHRSaFDi3FXJc+tLI6vqYaGzwgJo7WbzYzpHmv3v7WVR13KzQG/vJXDt8aOObOj7mzsQ8BQgK6+spp91Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732028464; c=relaxed/simple; bh=IosRVsOhXaWuKtna+S7TTj7J8IIDP2TBXfqtgenJkPY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QqU3e16KnTEbdaXPHTRoIto5MrJzppwZx7ou1CI93HuWSfQQFlvWt3xtiB74l3ILKSOxNeQdlqhyJRqyE54lyd02YpV2DB/07vDcSh/JGf2ZAUPoF7v+4AWTMO+EtvZw0b5ycZHmQ9oUd2vsU+7q68woKBqzus7yC4xLUvKQwus= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rHmW8pyz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rHmW8pyz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2C4EFC4CED2; Tue, 19 Nov 2024 15:01:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732028464; bh=IosRVsOhXaWuKtna+S7TTj7J8IIDP2TBXfqtgenJkPY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rHmW8pyzYESo0w1Bh0OvU2MjWhCyLjMvDfeLfvzyQteYRnJSV7OwbQUwfrh0iiJDc BnV8vzJEAabyNT7Q9lAzrjSMaZepbOzslZ3a8KcbwFs3s9IdjjAjZe4kADrV5qVUPj cZ5EQurVs5mDOVHCL7kJJBEl021RRganQhLXMo0TsriMR7zZW21nhVvoXIBdIYJro4 meyaK5vxsErcdbE4RyA76Azg3ld6aNV9oHt472Dh8rBWlkbVDqE9PpFA9ChNhiZ/ih JG+C2BmrgMHyV7llKWR2JsNl+7Py6nqhN7KHQaMk1zImgnDmOwqr45mrf83qB8SHHa bImfoWAJ22amg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DE76D44167; Tue, 19 Nov 2024 15:01:04 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Tue, 19 Nov 2024 16:00:08 +0100 Subject: [PATCH v5 02/16] net: driver: stmmac: Extend CSR calc support Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241119-upstream_s32cc_gmac-v5-2-7dcc90fcffef@oss.nxp.com> References: <20241119-upstream_s32cc_gmac-v5-0-7dcc90fcffef@oss.nxp.com> In-Reply-To: <20241119-upstream_s32cc_gmac-v5-0-7dcc90fcffef@oss.nxp.com> To: Maxime Coquelin , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vinod Koul , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Emil Renner Berthing , Minda Chen , Nicolas Ferre , Claudiu Beznea , Iyappan Subramanian , Keyur Chudgar , Quan Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, NXP S32 Linux Team , "Jan Petrous (OSS)" , Jacob Keller X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732028461; l=2225; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=50kRIgWTZi5wCMka5I1DSABnnyKmmvDBzkE8UY/BAAc=; b=pMklRc3dp+NTaxkgKq7mLlrrefkInnF9GNFsD5SvbHHqshUcFJtH3UvED4kFZ69nTWOQHBVTX uKHpEoqqbP9BHh40hpxQr935ovrjlsPOE4NcZG8dF3iTKl9fX4IenzL X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Add support for CSR clock range up to 800 MHz. Signed-off-by: Jan Petrous (OSS) Reviewed-by: Jacob Keller Reviewed-by: Russell King (Oracle) --- drivers/net/ethernet/stmicro/stmmac/common.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++++ include/linux/stmmac.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 684489156dce..e364cf99d1ff 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -257,6 +257,8 @@ struct stmmac_safety_stats { #define CSR_F_150M 150000000 #define CSR_F_250M 250000000 #define CSR_F_300M 300000000 +#define CSR_F_500M 500000000 +#define CSR_F_800M 800000000 #define MAC_CSR_H_FRQ_MASK 0x20 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 7bf275f127c9..85fa75fa6abe 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -324,6 +324,10 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) priv->clk_csr = STMMAC_CSR_150_250M; else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) priv->clk_csr = STMMAC_CSR_250_300M; + else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M)) + priv->clk_csr = STMMAC_CSR_300_500M; + else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M)) + priv->clk_csr = STMMAC_CSR_500_800M; } if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 75cbfb576358..865d0fe26f98 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -34,6 +34,8 @@ #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/124 */ +#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */ +#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */ /* MTL algorithms identifiers */ #define MTL_TX_ALGORITHM_WRR 0x0