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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3nybBDwzCO7JhkoDtOYNDVVH4m2FQ+yrzdOFaWdik/Z6VXV/lQCT5slB5nEs3jrzFnfcrakzrsepx4+gzexPAdJMtnI204ivKNFnx7U3c/Sa2L6k5SbXuQSazoNTtVEAQl246xp03/lfyVjvCChVZrzSoA0FfPm7zhaHjz1S7Dr4eoo7GFXw4BVzIRE3ha+TNqztSpXudf58A0qd+5fuu2AJLa6EeoWnJ4XlefH8KSVATtoGl3Tv+9gcJh6TVvl9LVFFLpvP8DHPQg73DWMZXW08FttIljcvVj/uE1RQzXaWOplGAZrcElZ+QVDHj/STUd5pwkVOHu1DXhx/k/KheuFn7R1qQpuJplN4ZI/fPQFgvxeCxBwn9e29xq+YxwOrMfgTp796AQexEzz4cPLV9OE4RSP3zPnP6qiwGspVq6j6QoWTteai/6pcGo5X5qXwJXWY/ljBXEFutt+SBz09XSCbMTxAd7ayR7WNRf+GB3bfmNywDRCykwURyaIyN9k0pk5P1PXtwJ2T5THWUgOQjQK++Q6BPELztFW27hvLBDa13OtERgqyij9Kvf72Lrx9HFYIxMLTAlc0dWYYmg/G0/P635Em5RPDvu+e4BRh3ucrDTQO+upV7Q/mwQws6clOHIuhvRHOB92dXO2x+hdu62oGmIjuKD3hc1i8S3x2ze0Ee1IxB2cMH+38t0Tgu5shhNZidbJxkAgri6bmiJ4WUiy4cKY08SKh/16kaMEXymI+6cknHGsglVQIGVFSuuB0iSVJiE2xoKL10EDy0WLJhp1VyhSkTlMWP9qwWSGDWO78+NrhVWAcZV7jeN+Rwlkmx2/Sgt7DeyEGSzYeYuUNCBfpQnRxb7jRVX+DORp0X7XQu64W4HKrocH/5+/lJeE4OPkgX4EUKvXf3sN7HuPRX2ELvrtnq3wzLQP99Q83FmWS7w73GNUhwqFwZUr8vgpoHMEYLvPTj6FVNv/I6JwzOgHCBO1XOS6faxhEI62TcV/Dktfits/cFY16NwjCriCm/OTKes1NlDmD9iTjh04ARHim7bJcXHq92V29cgCwB8hh0FeN+FGXiljzekQO9ePbZ6+R/zUnjb60MIj860Ne+bwaH32nNNjg7QEoO/THD7rqHiiATlCfFveNJ8RO/Ss4Mo7TF6ISL4a3sd5zXEMbWoenNKEILsAtAyUHUhAnmI/BapE0rwihtGAmLRa/d05PmhVyLxIe6cDA4AZ5ovsl98vwYbV4ylvOUyW6iHlPZOtaj3CoUnKpS45Y7ln0R17DvUBoLWzD1i3EcfLOnvx9H3g/K/9OtD1eT+FAWO7DSEjuvyUlGIBVFWSbiR5Ro8q4IMol1dKsFazHp7VIUQCNPl7no8yPU2RoXD3jwrgdG0QQnzVCCY+ce1RAnfCiAirGZkzqBk5dAfLo+x2bpEp0ff+yMvXBCJOdvHU2afqElkEir8XuxMzoEwKPIpzthz5dzOwc3Q+di0rJPO2BdpbLVXoqDUlKkmhhQyp7dts1s2Ub4g4pIMQsigTtXDHZdSnighc/MY9QfOwv2CHlqE+q564do0bPA1M3eZHQ+/e4N11sUw9WvkPtP7k0X0WRRoVb X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3b5f351c-bd11-4320-e658-08dd0df003e2 X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8676.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2024 07:57:46.6986 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4qfTOnJpxBnoxku4IrSgdK4nFJwbo9XWeLBha4Hv++bgQx128MxBBkRK8Lg6EDobYzAHhOmFUBFjK9YZGiAY9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB9401 Add "ref" clock to enable reference clock. To avoid breaking DT backwards compatibility, i.MX95 REF clock might be optional. Use devm_clk_get_optional() to fetch i.MX95 PCIe optional clocks in driver. If use external clock, ref clock should point to external reference. If use internal clock, CREF_EN in LAST_TO_REG controls reference output, which implement in drivers/clk/imx/clk-imx95-blk-ctl.c. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 385f6323e3ca..f7e928e0a018 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { const char *gpr; const char * const *clk_names; const u32 clks_cnt; + const u32 clks_optional_cnt; const u32 ltssm_off; const u32 ltssm_mask; const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; @@ -1306,9 +1307,8 @@ static int imx_pcie_probe(struct platform_device *pdev) struct device_node *np; struct resource *dbi_base; struct device_node *node = dev->of_node; - int ret; + int i, ret, req_cnt; u16 val; - int i; imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); if (!imx_pcie) @@ -1358,9 +1358,13 @@ static int imx_pcie_probe(struct platform_device *pdev) imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i]; /* Fetch clocks */ - ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks); + req_cnt = imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optional_cnt; + ret = devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks); if (ret) return ret; + imx_pcie->clks[req_cnt].clk = devm_clk_get_optional(dev, "ref"); + if (IS_ERR(imx_pcie->clks[req_cnt].clk)) + return PTR_ERR(imx_pcie->clks[req_cnt].clk); if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) { imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); @@ -1509,6 +1513,7 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"}; +static const char * const imx95_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux", "ref"}; static const struct imx_pcie_drvdata drvdata[] = { [IMX6Q] = { @@ -1623,8 +1628,9 @@ static const struct imx_pcie_drvdata drvdata[] = { [IMX95] = { .variant = IMX95, .flags = IMX_PCIE_FLAG_HAS_SERDES, - .clk_names = imx8mq_clks, - .clks_cnt = ARRAY_SIZE(imx8mq_clks), + .clk_names = imx95_clks, + .clks_cnt = ARRAY_SIZE(imx95_clks), + .clks_optional_cnt = 1, .ltssm_off = IMX95_PE0_GEN_CTRL_3, .ltssm_mask = IMX95_PCIE_LTSSM_EN, .mode_off[0] = IMX95_PE0_GEN_CTRL_1,