From patchwork Tue Nov 26 11:49:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ciprian Marian Costea X-Patchwork-Id: 13885826 Received: from EUR02-VI1-obe.outbound.protection.outlook.com (mail-vi1eur02on2087.outbound.protection.outlook.com [40.107.241.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9355A1BCA07 for ; Tue, 26 Nov 2024 11:50:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.241.87 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732621805; cv=fail; b=UuEdwzc1s7DNsUkgrzUgmu4O25q7/8qr1+tLVUVoq/EwpCQVWnR8r4Y8WgGQU6LXglYCNkpWMOC9Ho9gmxHOAijpbkvFlS4F2g5YrJKFo84VwCLWYiXdBf5XOkhSibY+aIKKrt9TaGgqOrnHuGhadpo367obARhhV8rsYSjxlIo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732621805; c=relaxed/simple; bh=ghYlrrpdO/U0GFlUgKLCeTLQf/z286Ld4c+VTyZ1XkM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=D4dhwSNWgivqPWuNSqJFnjtk9IooLwOVsVs+mcRCOPREe2LwF7rwog3piHHcILrvf0K2cu+HkpnZ9u0ZsEkvvkdjytGXiJzdCuMV901LygJDQO5olr+b+uqEqVDzFWB4LXEalcgKp79bZUtrJsD+3mK6BgqPCtMx0JUNT9d7cnU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=LAbLNKas; arc=fail smtp.client-ip=40.107.241.87 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="LAbLNKas" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tn+fK3blvtUbo+bxwmgVZhp3nhuF5Kkv7uESLbZtbZE0nF9bH4Tr3YuGXKJ2ET5giXtc2WbQIzyintaK3GZXS//8wpKBm16sgkNXdZmNSsF4n/7jp3PLqWkbaa4bfFiTkmwi9G9S6TdG5YQ7AhKUDy8aDpip8v8gm5fc7SvcFKyfikYnfxvS8g4gTdDuaWwHkofkfqQ4160RzlwXqt/xCBR6h7lbPm1IlJcOgUz/K0mfKwcwn08H72XNzipLlqXzZvqnrjeeL2oNIdOuU8ekqohnC2s8LEbmfbK+1LnOKT3uDulH2mC8Mr8wOf6ypPWpqUNtgTOOVVkmflOFTlCNOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sGT7f9f6ionItdWDsRmqGZGyk8+LLofWhC7Kl/ZQ24o=; b=dXb9dfmmGzeZbKpRfnjbybWNDAx+d2ncalJTPhaBD1F+lE0vI36Dfsoz5GkyOARY52xb3M4qhUB9rvV7N33eP5/mSvkFaw+aTRBIgyME1lwbTWaye8RKZCBWhqCACUsuclHUJjR91e8D8rNhcKDSe9t+JDCpxq8MzeNrI99el6q8F9a14WrXSRGMnuZVqKjpXsx5ZHDIasyA5uDYZKcCnIvYiP15C5jU4h7YZ9BwyjSD9Ab5kvZAg/CNnq3TXqSlZHugWYf3RviaxY6Vy/N3wlFp6RmQNLwk6poV6VdaI4pPWlaNsQl39R6NFNIQbobjnBH5XowWqV51QVJ9tUl23A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sGT7f9f6ionItdWDsRmqGZGyk8+LLofWhC7Kl/ZQ24o=; b=LAbLNKasWFt839r/a+s8qaouXq+/GcalBGVWVC9vtYr4NbsFdTeElfapHMqNEXWCyaSDlFaf8rENYIucU+CyJAfR3LDZWM3jfMkUnLX2UMnC0T6bEx0BbzoBv1JZ13dexlqzLXGZ3bu3BAhKRnhB0So/auK/oZQB2mU2rh4r7iM9R7mQiVyMZQKwxd8ry7b1BmvxfS2DSNLjsu4R8dneYeDUgHXPrOxMi1bVJInIakXNXCuOdbuhtzd2uqVrmdM5pZEp0Y7KsrQcp3+4HSk6NoA0MuiAmZnfKkpqqP9fbU2U1hhbayzJbMxY9Tio4BsEk63ShGUS4d01OW9+RmIZ5g== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) by PA1PR04MB10294.eurprd04.prod.outlook.com (2603:10a6:102:44d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8182.21; Tue, 26 Nov 2024 11:49:58 +0000 Received: from DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd]) by DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd%6]) with mapi id 15.20.8182.019; Tue, 26 Nov 2024 11:49:58 +0000 From: Ciprian Costea To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, NXP S32 Linux , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Ciprian Marian Costea , Bogdan Hamciuc , Ghennadi Procopciuc Subject: [PATCH v5 2/4] rtc: s32g: add NXP S32G2/S32G3 SoC support Date: Tue, 26 Nov 2024 13:49:38 +0200 Message-ID: <20241126114940.421143-3-ciprianmarian.costea@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126114940.421143-1-ciprianmarian.costea@oss.nxp.com> References: <20241126114940.421143-1-ciprianmarian.costea@oss.nxp.com> X-ClientProxiedBy: BEXP281CA0013.DEUP281.PROD.OUTLOOK.COM (2603:10a6:b10::23) To DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|PA1PR04MB10294:EE_ X-MS-Office365-Filtering-Correlation-Id: bcd0cf8b-f4ae-40f6-eff4-08dd0e1073c7 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|366016; X-Microsoft-Antispam-Message-Info: =?utf-8?q?G6yOK9JP8tzaos/CdlKOz/v/I3iDUDZ?= =?utf-8?q?I75sgf5cEij9TnOGbk6CulOa7LHzVc0acIQ8Cy1BKNiztMhYm1fTf92T9ydvYavT8?= =?utf-8?q?AtlpadTE3WNitjvWmE/YN7lX+pjfN1qbLnIyJ/6IBWXfH6H0aES6i87UfNOfL+9LH?= =?utf-8?q?smYc8njnAdZhhCOsKKg3BR5Tp3wc+OLOLue708DLe1wLsZ1N9MdXmVrQxJ+qwX20Z?= =?utf-8?q?8esypBgYlvV0LpCD1bMOsoKT1GUhOeQhQabUkcUwTtqM20LozPR1oorpFhq2PInWu?= =?utf-8?q?VZrJEdCdPD9AtRDkklC350BKAYYgAd+p78hKE3+yzwsP/TtJaitl0QQtO1QELV3qg?= =?utf-8?q?MDSOmYIds9k+J+0dnzOqwRwypnBYQC4FT/b7sb3oG6F7arGLVO8yMONkqFji4qv2W?= =?utf-8?q?bpyvT7UWEVwrmTNX+hh1MtMS55ndBYHJKqO8deIx0nPJd+LMEU/WoFPljuYmIm4F0?= =?utf-8?q?r/qWgeMk/0u2vhFq89hskcfzU2qMIv2JjWGFSpZclX3G1zHEamRLnEVui3KI1iBHC?= =?utf-8?q?Bo2n/RopeybcJ7kV+fRscmksiX+F6TAxHlHYgYfgNc5pzm7ZcHv4l2HPpPyaVbDPs?= =?utf-8?q?CeGsxrFR8t/LORFa3kW/Zd1+1I7XAU+WpOPPlhOm6Ylss3A5Pm+/emNZJ++Hijb99?= =?utf-8?q?pnAcIaqliPc9DdOG9pj/D5VapWDgMNsbUcPF7mUcw+4LztCBZvBbgATH3OCFgT+1i?= =?utf-8?q?MDJorg71bx+5sZR7oMAMbPm7tHtujPngp5v0jkeS/+9wbtkGqo58Wn/CTQeM0FLSh?= =?utf-8?q?EdoSn0eJadlkzQz0IOFH2lA8oXhP04GDtqB/CzsvK8ipHOmTkrRddy8s/nZ9XbOA4?= =?utf-8?q?f+TWkw3donVC9gEDawptnKfL6hdep5+IbjSPlw72ho9JlnNYGYbrNOq5Lu1bWr6cm?= =?utf-8?q?5kDWtFg7OpaKqeXvgzpkHhMKNnpU8PPCAjFpZXzeHTKGn3azG+4xehkrzR2/dy0JI?= =?utf-8?q?p50EPBd6lgmJPHVSLYZcaYVvFBps+RFmH65ng+ZfWRHXXZ1tLkQkqxUDqv1Q5zrAx?= =?utf-8?q?GUDucFferaJuB5QpnQ2ewkMzQkQvlzbeKevzpMdqOaBFHzGkEmzJgDI21Vz3yLBKy?= =?utf-8?q?pwFUvHYQ21pAQO7lKfnQwPxWV+2w8FeXNYIZmr4Rg0meBG3T7pTJ7nt8Aq8XspnbB?= =?utf-8?q?jtRR1l6xIHiou+wXOrD5GiL8WHrENKvKL1FKsQT5gHKR11QfzbEWJBkmjWcuCejdA?= =?utf-8?q?3xy38ETLIMUhLRl6xdRvjiTN0e7aunJYGvXitbry8TJKnVNvcy93IPXjEcYrz3jF/?= =?utf-8?q?7NBTkOJf7XcNZ6h4BvImKqVESeYNOq/Ncrg=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9251.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(366016);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?o+wRGh6RUQfv5GL0ZUoCw5MtO8wc?= =?utf-8?q?iBHJTVKoSQUf+zL7ojM4bWKFI/6DLXkaY3n0Iq4WXV1sgmEhz+qqquCStVlC6VCMu?= =?utf-8?q?T/0Vqv7xwgzOBK2SIC0fcC22bB8UUlsOKF2y7IhzA9aCuAPm054+ua8TBweFCMcoY?= =?utf-8?q?ieq9HU4dfBtysmlbkFbMu4RMDt795ceH6dFhri7ZaZfEms/pwKha4pgJue/T8p/Ry?= =?utf-8?q?iQNTdiWmyPz7rzg3H75iIwnghUAYiLd1HOz3RH7O/5dhqu78EGPQmd+bjXWHp2rI9?= =?utf-8?q?rbrH4ihYOgtz6X78+yZrFi+NQ/bUjrJUfPtUMxIHRUfRjebLzsJyfaFjaXZVw8QEs?= =?utf-8?q?BL3UR/ESEyHqIm4hZGEMXZxtcgpsoXg+rhOH0XdMbLV4/K0E7/FW2mf2nGrauuwY4?= =?utf-8?q?/ElbM609oQNXyF/VhJelaqyCYWe6qoZ6rZSs6STrp/HNA69zBS285TvWlEt/DhwcF?= =?utf-8?q?SzyYrVjrjUZ6w8ZegUAEXDrawTWba8uySyrM8E8HpTT6w2b6UlYlIYGoXHCsoAYwo?= =?utf-8?q?tQUuil6a3QN1KxxOn4dP5JCe5i/s2Zq7RPdp1ALmKk7/fvgFRifXwQRwi53V6uAQ8?= =?utf-8?q?pqnLG+kLamq3X2/JWuQMZpLEsTKr/e+Qak3MyEtztrWWi76uO7pEF6GmhFb6w1fSN?= =?utf-8?q?oQwlsKeesV7v+hz+r33TQf07W9BMdpdC5VWc/FOGcT87BqohFkR/ekzbndwWZ2b2V?= =?utf-8?q?HBOStjTuqx2elGAYl+l8sC2SuTnUsqr5uaIyteFQj4Jgu/DrDrTFSrYTolYUAHk4C?= =?utf-8?q?BxEJUzRx4zm/07mCObByeKU0JGl/qJEkYULEWKODNd1UA+Zuuy2n6YzH+9qHsimym?= =?utf-8?q?VMC3hRbr5g1s2NV+X/InWvbmZvfH3/sWyYuVDLAoFJRPOc6SFblqLrJvXIXrQBRM3?= =?utf-8?q?spBcj3tC9B7ZUY6MJF9c2eIGXU00fGHdRZoJ+SVOFVk91wIC3v5Bul1lheFPmcOBZ?= =?utf-8?q?hcW4tlJmAlq2kdDbrzBY/ojdUsdPJ73921KsEdamycJckbSLVSxWD+I90DcCf/JAx?= =?utf-8?q?1TyiouSELfy9UzHmSGIqFMfaRwozeB2DuHAEzRKPVN3EXuT1OT6u7/OiUcLqI6JOp?= =?utf-8?q?l8mUT2/L8SXwrcRzP/q7wUd+VG1rLliwNg0Kj29xv8EM8Z0vNHUdk6ohuLgMMsVQS?= =?utf-8?q?W5JOPZn0q1w8msFgYo8p3r6ZKFN7txntsQif4+ZkDaqrjd1XG9jby3Lk7lr9NgBfs?= =?utf-8?q?UOBPBIuFyVps1CmbPzPi0BJA9MWPlYMKiIH6M2t/GaUaVnMYW29eb65NVbK7/+1ow?= =?utf-8?q?zYbEEXlSod2/uMJF9lH8hMRNPsaZplQ7Ig3vWnB6zYJAw92xbzFJ3c/OZTl0vYJvK?= =?utf-8?q?Gq39vtxQBchKfmBvZxty95ooudFsW+8uewyqVQ/vWg2geAwvVBKWsDocsFyXH83QH?= =?utf-8?q?SvhzIV4hLlmxQ0IEHaIcqe9Pu9AYhoQD9GUE68WVnJtFUzcF7sj0Gu/4eqHma7rHD?= =?utf-8?q?gHJNC0Hs7sqJ620ESJrobM+01YpFwx4zyMBpbCJEokhcpzcjS1TXxTGqceLii+hS6?= =?utf-8?q?OOoxM1G5UYU+PNQTReGOct4PHT6qKdik9w=3D=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: bcd0cf8b-f4ae-40f6-eff4-08dd0e1073c7 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9251.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2024 11:49:58.2726 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PZAYSRywo//xYG73V8DBlaFuOXdZbiFJ0F+37R+BS+iJ/aZEJNwwmaJC1JpkByNhG+qd8G5WkWoaqs7XYfmTFHroCekp2Bxv60lkQyJJFFk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR04MB10294 From: Ciprian Marian Costea Add a RTC driver for NXP S32G2/S32G3 SoCs. RTC tracks clock time during system suspend. It can be a wakeup source for the S32G2/S32G3 SoC based boards. The RTC module from S32G2/S32G3 is not battery-powered and it is not kept alive during system reset. Co-developed-by: Bogdan Hamciuc Signed-off-by: Bogdan Hamciuc Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Signed-off-by: Ciprian Marian Costea --- drivers/rtc/Kconfig | 11 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-s32g.c | 554 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 566 insertions(+) create mode 100644 drivers/rtc/rtc-s32g.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index e87c3d74565c..18fc3577f6cd 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -2054,4 +2054,15 @@ config RTC_DRV_SSD202D This driver can also be built as a module, if so, the module will be called "rtc-ssd20xd". +config RTC_DRV_S32G + tristate "RTC driver for S32G2/S32G3 SoCs" + depends on ARCH_S32 || COMPILE_TEST + depends on COMMON_CLK + help + Say yes to enable RTC driver for platforms based on the + S32G2/S32G3 SoC family. + + This RTC module can be used as a wakeup source. + Please note that it is not battery-powered. + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 8ee79cb18322..a63d010a753c 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -158,6 +158,7 @@ obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c new file mode 100644 index 000000000000..ad78423783da --- /dev/null +++ b/drivers/rtc/rtc-s32g.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTCC_OFFSET 0x4ul +#define RTCS_OFFSET 0x8ul +#define RTCCNT_OFFSET 0xCul +#define APIVAL_OFFSET 0x10ul +#define RTCVAL_OFFSET 0x14ul + +/* RTCC fields */ +#define RTCC_CNTEN BIT(31) +#define RTCC_RTCIE_SHIFT 30 +#define RTCC_RTCIE BIT(RTCC_RTCIE_SHIFT) +#define RTCC_APIEN BIT(15) +#define RTCC_APIIE BIT(14) +#define RTCC_CLKSEL_OFFSET 12 +#define RTCC_CLKSEL_MASK GENMASK(13, 12) +#define RTCC_CLKSEL(n) (((n) << 12) & RTCC_CLKSEL_MASK) +#define RTCC_DIV512EN BIT(11) +#define RTCC_DIV32EN BIT(10) + +/* RTCS fields */ +#define RTCS_RTCF BIT(29) +#define RTCS_INV_RTC BIT(18) +#define RTCS_APIF BIT(13) + +#define RTCCNT_MAX_VAL GENMASK(31, 0) +#define RTC_SYNCH_TIMEOUT (100 * USEC_PER_MSEC) + +#define RTC_CLK_MUX_SIZE 4 + +/* + * S32G2 and S32G3 SoCs have RTC clock source 1 reserved and + * should not be used. + */ +#define RTC_QUIRK_SRC1_RESERVED BIT(2) + +enum { + RTC_CLK_SRC0, + RTC_CLK_SRC1, + RTC_CLK_SRC2, + RTC_CLK_SRC3 +}; + +enum { + DIV1 = 1, + DIV32 = 32, + DIV512 = 512, + DIV512_32 = 16384 +}; + +static const char *rtc_clk_src[RTC_CLK_MUX_SIZE] = { + "source0", + "source1", + "source2", + "source3" +}; + +struct rtc_time_base { + s64 sec; + u64 cycles; + struct rtc_time tm; +}; + +struct rtc_priv { + struct rtc_device *rdev; + void __iomem *rtc_base; + struct clk *ipg; + struct clk *clk_src; + const struct rtc_soc_data *rtc_data; + struct rtc_time_base base; + u64 rtc_hz; + int dt_irq_id; + int clk_src_idx; +}; + +struct rtc_soc_data { + u32 clk_div; + u32 quirks; +}; + +static const struct rtc_soc_data rtc_s32g2_data = { + .clk_div = DIV512, + .quirks = RTC_QUIRK_SRC1_RESERVED, +}; + +static int is_src1_reserved(struct rtc_priv *priv) +{ + return priv->rtc_data->quirks & RTC_QUIRK_SRC1_RESERVED; +} + +static u64 cycles_to_sec(u64 hz, u64 cycles) +{ + return div_u64(cycles, hz); +} + +/** + * Convert a number of seconds to a value suitable for RTCVAL in our clock's + * current configuration. + * @rtcval: The value to go into RTCVAL[RTCVAL] + * Returns: 0 for success, -EINVAL if @seconds push the counter past the + * 32bit register range + */ +static int sec_to_rtcval(const struct rtc_priv *priv, + unsigned long seconds, u32 *rtcval) +{ + u32 delta_cnt; + + if (!seconds || seconds > cycles_to_sec(priv->rtc_hz, RTCCNT_MAX_VAL)) + return -EINVAL; + + /* + * RTCCNT is read-only; we must return a value relative to the + * current value of the counter (and hope we don't linger around + * too much before we get to enable the interrupt) + */ + delta_cnt = seconds * priv->rtc_hz; + *rtcval = delta_cnt + ioread32(priv->rtc_base + RTCCNT_OFFSET); + + return 0; +} + +static irqreturn_t s32g_rtc_handler(int irq, void *dev) +{ + struct rtc_priv *priv = platform_get_drvdata(dev); + u32 status; + + status = ioread32(priv->rtc_base + RTCS_OFFSET); + + if (status & RTCS_RTCF) { + iowrite32(0x0, priv->rtc_base + RTCVAL_OFFSET); + rtc_update_irq(priv->rdev, 1, RTC_AF); + } + + if (status & RTCS_APIF) + rtc_update_irq(priv->rdev, 1, RTC_PF); + + iowrite32(status, priv->rtc_base + RTCS_OFFSET); + + return IRQ_HANDLED; +} + +static s64 s32g_rtc_get_time_or_alrm(struct rtc_priv *priv, + u32 offset) +{ + u32 counter; + + counter = ioread32(priv->rtc_base + offset); + + if (counter < priv->base.cycles) + return -EINVAL; + + counter -= priv->base.cycles; + + return priv->base.sec + cycles_to_sec(priv->rtc_hz, counter); +} + +static int s32g_rtc_read_time(struct device *dev, + struct rtc_time *tm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + s64 sec; + + sec = s32g_rtc_get_time_or_alrm(priv, RTCCNT_OFFSET); + if (sec < 0) + return -EINVAL; + + rtc_time64_to_tm(sec, tm); + + return 0; +} + +static int s32g_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 rtcc, rtccnt, rtcval; + s64 sec; + + sec = s32g_rtc_get_time_or_alrm(priv, RTCVAL_OFFSET); + if (sec < 0) + return -EINVAL; + + rtc_time64_to_tm(sec, &alrm->time); + + rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + alrm->enabled = sec && (rtcc & RTCC_RTCIE); + + alrm->pending = 0; + if (alrm->enabled) { + rtccnt = ioread32(priv->rtc_base + RTCCNT_OFFSET); + rtcval = ioread32(priv->rtc_base + RTCVAL_OFFSET); + + if (rtccnt < rtcval) + alrm->pending = 1; + } + + return 0; +} + +static int s32g_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 rtcc; + + if (!priv->dt_irq_id) + return -EIO; + + rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + if (enabled) + rtcc |= RTCC_RTCIE; + + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); + + return 0; +} + +static int s32g_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + struct rtc_time time_crt; + long long t_crt, t_alrm; + u32 rtcval, rtcs; + int ret = 0; + + iowrite32(0x0, priv->rtc_base + RTCVAL_OFFSET); + + t_alrm = rtc_tm_to_time64(&alrm->time); + + /* + * Assuming the alarm is being set relative to the same time + * returned by our s32g_rtc_read_time callback + */ + ret = s32g_rtc_read_time(dev, &time_crt); + if (ret) + return ret; + + t_crt = rtc_tm_to_time64(&time_crt); + ret = sec_to_rtcval(priv, t_alrm - t_crt, &rtcval); + if (ret) { + dev_warn(dev, "Alarm is set too far in the future\n"); + return -ERANGE; + } + + ret = read_poll_timeout(ioread32, rtcs, !(rtcs & RTCS_INV_RTC), + 0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET); + if (ret) + return ret; + + iowrite32(rtcval, priv->rtc_base + RTCVAL_OFFSET); + + return 0; +} + +static int s32g_rtc_set_time(struct device *dev, + struct rtc_time *time) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + + priv->base.cycles = ioread32(priv->rtc_base + RTCCNT_OFFSET); + priv->base.sec = rtc_tm_to_time64(time); + + return 0; +} + +/* + * Disable the 32-bit free running counter. + * This allows Clock Source and Divisors selection + * to be performed without causing synchronization issues. + */ +static void s32g_rtc_disable(struct rtc_priv *priv) +{ + u32 rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + + rtcc &= ~RTCC_CNTEN; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static void s32g_rtc_enable(struct rtc_priv *priv) +{ + u32 rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + + rtcc |= RTCC_CNTEN; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static int rtc_clk_src_setup(struct rtc_priv *priv) +{ + u32 rtcc = 0; + + switch (priv->clk_src_idx) { + case RTC_CLK_SRC0: + rtcc |= RTCC_CLKSEL(RTC_CLK_SRC0); + break; + case RTC_CLK_SRC1: + if (is_src1_reserved(priv)) + return -EOPNOTSUPP; + rtcc |= RTCC_CLKSEL(RTC_CLK_SRC1); + break; + case RTC_CLK_SRC2: + rtcc |= RTCC_CLKSEL(RTC_CLK_SRC2); + break; + case RTC_CLK_SRC3: + rtcc |= RTCC_CLKSEL(RTC_CLK_SRC3); + break; + default: + return -EINVAL; + } + + switch (priv->rtc_data->clk_div) { + case DIV512_32: + rtcc |= RTCC_DIV512EN; + rtcc |= RTCC_DIV32EN; + break; + case DIV512: + rtcc |= RTCC_DIV512EN; + break; + case DIV32: + rtcc |= RTCC_DIV32EN; + break; + case DIV1: + break; + default: + return -EINVAL; + } + + rtcc |= RTCC_RTCIE; + /* + * Make sure the CNTEN is 0 before we configure + * the clock source and dividers. + */ + s32g_rtc_disable(priv); + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); + s32g_rtc_enable(priv); + + return 0; +} + +static const struct rtc_class_ops rtc_ops = { + .read_time = s32g_rtc_read_time, + .set_time = s32g_rtc_set_time, + .read_alarm = s32g_rtc_read_alarm, + .set_alarm = s32g_rtc_set_alarm, + .alarm_irq_enable = s32g_rtc_alarm_irq_enable, +}; + +static int rtc_clk_dts_setup(struct rtc_priv *priv, + struct device *dev) +{ + int i; + + priv->ipg = devm_clk_get_enabled(dev, "ipg"); + if (IS_ERR(priv->ipg)) + return dev_err_probe(dev, PTR_ERR(priv->ipg), + "Failed to get 'ipg' clock\n"); + + for (i = 0; i < RTC_CLK_MUX_SIZE; i++) { + priv->clk_src = devm_clk_get_enabled(dev, rtc_clk_src[i]); + if (!IS_ERR(priv->clk_src)) { + priv->clk_src_idx = i; + break; + } + } + + if (IS_ERR(priv->clk_src)) + return dev_err_probe(dev, PTR_ERR(priv->clk_src), + "Failed to get rtc module clock source\n"); + + return 0; +} + +static int s32g_rtc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtc_priv *priv; + int ret = 0; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->rtc_data = of_device_get_match_data(dev); + if (!priv->rtc_data) + return -ENODEV; + + priv->rtc_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->rtc_base)) + return PTR_ERR(priv->rtc_base); + + device_init_wakeup(dev, true); + + ret = rtc_clk_dts_setup(priv, dev); + if (ret) + return ret; + + priv->rdev = devm_rtc_allocate_device(dev); + if (IS_ERR(priv->rdev)) + return PTR_ERR(priv->rdev); + + ret = rtc_clk_src_setup(priv); + if (ret) + return ret; + + priv->rtc_hz = clk_get_rate(priv->clk_src); + if (!priv->rtc_hz) + return dev_err_probe(dev, -EINVAL, "Failed to get RTC frequency\n"); + + priv->rtc_hz /= priv->rtc_data->clk_div; + + platform_set_drvdata(pdev, priv); + priv->rdev->ops = &rtc_ops; + + priv->dt_irq_id = platform_get_irq(pdev, 0); + if (priv->dt_irq_id < 0) + return priv->dt_irq_id; + + ret = devm_request_irq(dev, priv->dt_irq_id, + s32g_rtc_handler, 0, dev_name(dev), pdev); + if (ret) { + dev_err(dev, "Request interrupt %d failed, error: %d\n", + priv->dt_irq_id, ret); + goto disable_rtc; + } + + ret = devm_rtc_register_device(priv->rdev); + if (ret) + goto disable_rtc; + + return 0; + +disable_rtc: + s32g_rtc_disable(priv); + return ret; +} + +static void enable_api_irq(struct device *dev, unsigned int enabled) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 api_irq = RTCC_APIEN | RTCC_APIIE; + u32 rtcc; + + rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + if (enabled) + rtcc |= api_irq; + else + rtcc &= ~api_irq; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static int s32g_rtc_suspend(struct device *dev) +{ + struct rtc_priv *init_priv = dev_get_drvdata(dev); + struct rtc_priv priv; + long long base_sec; + u32 rtcval, rtccnt; + int ret = 0; + u32 sec; + + if (!device_may_wakeup(dev)) + return 0; + + /* Save last known timestamp */ + ret = s32g_rtc_read_time(dev, &init_priv->base.tm); + if (ret) + return ret; + + /* + * Use a local copy of the RTC control block to + * avoid restoring it on resume path. + */ + memcpy(&priv, init_priv, sizeof(priv)); + + rtccnt = ioread32(init_priv->rtc_base + RTCCNT_OFFSET); + rtcval = ioread32(init_priv->rtc_base + RTCVAL_OFFSET); + sec = cycles_to_sec(init_priv->rtc_hz, rtcval - rtccnt); + + /* Adjust for the number of seconds we'll be asleep */ + base_sec = rtc_tm_to_time64(&init_priv->base.tm); + base_sec += sec; + rtc_time64_to_tm(base_sec, &init_priv->base.tm); + + /* Reset RTC to prevent overflow. + * RTCCNT (RTC Counter) cannot be individually reset + * since it is RO (read-only). + */ + s32g_rtc_disable(&priv); + s32g_rtc_enable(&priv); + + ret = sec_to_rtcval(&priv, sec, &rtcval); + if (ret) { + dev_warn(dev, "Alarm is too far in the future\n"); + return -ERANGE; + } + + enable_api_irq(dev, 1); + iowrite32(rtcval, priv.rtc_base + APIVAL_OFFSET); + iowrite32(0, priv.rtc_base + RTCVAL_OFFSET); + + return ret; +} + +static int s32g_rtc_resume(struct device *dev) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + int ret; + + if (!device_may_wakeup(dev)) + return 0; + + /* Disable wake-up interrupts */ + enable_api_irq(dev, 0); + + ret = rtc_clk_src_setup(priv); + if (ret) + return ret; + + /* + * Now RTCCNT has just been reset, and is out of sync with priv->base; + * reapply the saved time settings. + */ + return s32g_rtc_set_time(dev, &priv->base.tm); +} + +static const struct of_device_id rtc_dt_ids[] = { + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, + { /* sentinel */ }, +}; + +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, + s32g_rtc_suspend, s32g_rtc_resume); + +static struct platform_driver s32g_rtc_driver = { + .driver = { + .name = "s32g-rtc", + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), + .of_match_table = rtc_dt_ids, + }, + .probe = s32g_rtc_probe, +}; +module_platform_driver(s32g_rtc_driver); + +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); +MODULE_LICENSE("GPL");