[3/3] arm64: dts: imx8mm-phyboard-polis-peb-av-10: Set custom lvds_vcom

Commit Message

Andrej Picej Nov. 27, 2024, 10:30 a.m. UTC

Set custom differential output voltage for LVDS, to fulfill requirements
of the connected display. LVDS diferential voltage for data-lanes and
clock output has to be between 200 mV and 600 mV.
Driver sets 200 Ohm near-end termination by default and since
LVDS_VCOM_CHA_LVDS_VOD_SWING (0x19) [3:2] sets both data-lane and clock
output voltage we have to set the register to the value of 0x0C (0b11 <<
2):
- Steady-state differential output voltage for LVDS data-lanes:
  min: 300 mV, typ: 402 mV, max: 511 mV
- Steady-state differential output voltage for LVDS clock lane:
  min: 234 mV, typ: 314 mV, max: 399 mV

Signed-off-by: Andrej Picej <[e-mail]>
---
 .../boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso      | 1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
index a9de42cf14be..709b555ca753 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
@@ -179,6 +179,7 @@  port@0 {
 			bridge_in: endpoint {
 				remote-endpoint = <&dsi_out>;
 				data-lanes = <1 2 3 4>;
+				ti,lvds-vcom = <0x0C>;
 			};
 		};