Message ID | 20241214172549.8842-8-apatel@ventanamicro.com (mailing list archive) |
---|---|
State | New |
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Sat, 14 Dec 2024 09:26:52 -0800 (PST) From: Anup Patel <apatel@ventanamicro.com> To: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <maz@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Andrew Lunn <andrew@lunn.ch>, Gregory Clement <gregory.clement@bootlin.com>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Atish Patra <atishp@atishpatra.org>, Andrew Jones <ajones@ventanamicro.com>, Sunil V L <sunilvl@ventanamicro.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH v2 07/11] RISC-V: Enable GENERIC_PENDING_IRQ and GENERIC_PENDING_IRQ_CHIPFLAGS Date: Sat, 14 Dec 2024 22:55:45 +0530 Message-ID: <20241214172549.8842-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241214172549.8842-1-apatel@ventanamicro.com> References: <20241214172549.8842-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: <imx.lists.linux.dev> List-Subscribe: <mailto:imx+subscribe@lists.linux.dev> List-Unsubscribe: <mailto:imx+unsubscribe@lists.linux.dev> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
Series |
RISC-V IMSIC driver improvements
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expand
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diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d4a7ca0388c0..adc878f029fb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -110,6 +110,8 @@ config RISCV select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL select GENERIC_LIB_DEVMEM_IS_ALLOWED + select GENERIC_PENDING_IRQ if SMP + select GENERIC_PENDING_IRQ_CHIPFLAGS if SMP select GENERIC_PCI_IOMAP select GENERIC_PTDUMP if MMU select GENERIC_SCHED_CLOCK
Enable GENERIC_PENDING_IRQ and GENERIC_PENDING_IRQ_CHIPFLAGS for RISC-V so that RISC-V irqchips can support delayed irq mirgration in the interrupt context. Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- arch/riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+)