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In addition, because all ENETC instances share MDIO bus, so enable EMDIO at the same time. Signed-off-by: Wei Fang --- .../boot/dts/freescale/imx95-19x19-evk.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 6086cb7fa5a0..e838234c8317 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -38,6 +38,7 @@ aliases { mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; + ethernet0 = &enetc_port0; }; bt_sco_codec: audio-codec-bt-sco { @@ -428,6 +429,33 @@ &wdog3 { status = "okay"; }; +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + realtek,clkout-disable; + }; +}; + &scmi_iomuxc { pinctrl_flexspi1: flexspi1grp { fsl,pins = < @@ -665,6 +693,30 @@ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_emdio: emdiogrp{ + fsl,pins = < + IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; }; &thermal_zones {