@@ -413,8 +413,10 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
res->name = "msg";
res->flags = win->res->flags | IORESOURCE_BUSY;
- if (!devm_request_resource(pci->dev, win->res, res))
+ if (!devm_request_resource(pci->dev, win->res, res)) {
pp->msg_res = res;
+ pp->msg_parent_bus_offset = win->parent_bus_offset;
+ }
}
}
@@ -427,6 +429,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
struct resource_entry *win;
struct pci_host_bridge *bridge;
struct resource *res;
+ int index;
int ret;
raw_spin_lock_init(&pp->lock);
@@ -448,6 +451,26 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
if (IS_ERR(pp->va_cfg0_base))
return PTR_ERR(pp->va_cfg0_base);
+ if (pci->use_parent_dt_ranges) {
+ if (pci->ops->cpu_addr_fixup) {
+ dev_err(dev, "Use parent bus DT ranges, cpu_addr_fixup() must be removed\n");
+ return -EINVAL;
+ }
+
+ index = of_property_match_string(np, "reg-names", "config");
+ if (index < 0)
+ return -EINVAL;
+
+ /*
+ * Retrieve the parent bus address of PCI config space.
+ * If the parent bus ranges in the device tree provide
+ * the correct address conversion information, set
+ * 'use_parent_dt_ranges' to true, The
+ * 'cpu_addr_fixup()' can be eliminated.
+ */
+ of_property_read_reg(np, index, &pp->cfg0_base, NULL);
+ }
+
bridge = devm_pci_alloc_host_bridge(dev, 0);
if (!bridge)
return -ENOMEM;
@@ -460,6 +483,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
pp->io_size = resource_size(win->res);
pp->io_bus_addr = win->res->start - win->offset;
pp->io_base = pci_pio_to_address(win->res->start);
+ /* In case ranges in pci node provide wrong information */
+ if (pci->use_parent_dt_ranges)
+ pp->io_base -= win->parent_bus_offset;
}
/* Set default bus ops */
@@ -739,6 +765,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
atu.parent_bus_addr = entry->res->start;
atu.pci_addr = entry->res->start - entry->offset;
+ /* In case ranges in pci node provide wrong information */
+ if (pci->use_parent_dt_ranges)
+ atu.parent_bus_addr -= entry->parent_bus_offset;
+
/* Adjust iATU size if MSG TLP region was allocated before */
if (pp->msg_res && pp->msg_res->parent == entry->res)
atu.size = resource_size(entry->res) -
@@ -902,7 +932,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
atu.size = resource_size(pci->pp.msg_res);
atu.index = pci->pp.msg_atu_index;
- atu.parent_bus_addr = pci->pp.msg_res->start;
+ atu.parent_bus_addr = pci->pp.msg_res->start - pci->pp.msg_parent_bus_offset;
ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret)
@@ -841,6 +841,15 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
pci->region_align = 1 << fls(min);
pci->region_limit = (max << 32) | (SZ_4G - 1);
+ if (pci->ops && pci->ops->cpu_addr_fixup) {
+ /*
+ * If the parent 'ranges' property in DT correctly describes
+ * the address translation, cpu_addr_fixup() callback is not
+ * needed.
+ */
+ dev_warn_once(pci->dev, "cpu_addr_fixup() usage detected. Please fix DT!\n");
+ }
+
dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n",
dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F",
pci->num_ob_windows, pci->num_ib_windows,
@@ -380,6 +380,7 @@ struct dw_pcie_rp {
bool use_atu_msg;
int msg_atu_index;
struct resource *msg_res;
+ resource_size_t msg_parent_bus_offset;
bool use_linkup_irq;
};
@@ -465,6 +466,13 @@ struct dw_pcie {
struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];
struct gpio_desc *pe_rst;
bool suspended;
+ /*
+ * This flag indicates that the vendor driver uses devicetree 'ranges'
+ * property to allow iATU to use the Intermediate Address (IA) for
+ * outbound mapping. Using this flag also avoids the usage of
+ * 'cpu_addr_fixup' callback implementation in the driver.
+ */
+ bool use_parent_dt_ranges;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
parent_bus_offset in resource_entry can indicate address information just ahead of PCIe controller. Most system's bus fabric use 1:1 map between input and output address. but some hardware like i.MX8QXP doesn't use 1:1 map. See below diagram: ┌─────────┐ ┌────────────┐ ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ 0x7ff8_0000─┼───┘ │ │ │ │ │ │ │ │ │ │ │ │ │ PCI Addr 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► │ │ │ │ │ 0 0x7000_0000─┼────────►├─────────┐ │ │ │ └─────────┘ │ └──────► CfgSpace ─┼────────────► BUS Fabric │ │ │ 0 │ │ │ └──────────► MemSpace ─┼────────────► IA: 0x8000_0000 │ │ 0x8000_0000 └────────────┘ bus@5f000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; Term Intermediate address (IA) here means the address just before PCIe controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can be removed. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- chagne from v8 to v9 - use resoure_entry parent_bus_offset to simple code logic - add check for use_parent_dt_ranges and cpu_addr_fixup to make sure only one set. Change from v7 to v8 - Add dev_warning_once at dw_pcie_iatu_detect() to reminder cpu_addr_fixup() user to correct their code - use 'use_parent_dt_ranges' control enable use dt parent bus node ranges. - rename dw_pcie_get_untranslate_addr to dw_pcie_get_parent_addr(). - of_property_read_reg() already have comments, so needn't add more. - return actual err code from function Change from v6 to v7 Add a resource_size_t parent_bus_addr local varible to fix 32bit build error. | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/ Chagne from v5 to v6 -add comments for of_property_read_reg(). Change from v4 to v5 - remove confused 0x5f00_0000 range in sample dts. - reorder address at above diagram. Change from v3 to v4 - none Change from v2 to v3 - %s/cpu_untranslate_addr/parent_bus_addr/g - update diagram. - improve commit message. Change from v1 to v2 - update because patch1 change get untranslate address method. - add using_dtbus_info in case break back compatibility for exited platform. --- drivers/pci/controller/dwc/pcie-designware-host.c | 34 +++++++++++++++++++++-- drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++ drivers/pci/controller/dwc/pcie-designware.h | 8 ++++++ 3 files changed, 49 insertions(+), 2 deletions(-)