From patchwork Fri Feb 7 08:36:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13964639 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 524C01ADC81 for ; Fri, 7 Feb 2025 08:37:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738917462; cv=none; b=E/x6MPPN8BCRcjRFfKgGmhRccuxW/ayOhcylVZK7rFXW6qvROs7dDdQ44UuVikgqH8bUQ+7kqZKKN4TaWw82S/tHFrxwVY3ZZ39wW1k/4AkgIDKF7wU8+sFDAeYMJQCmqPbrOtnFisi/4sJZFgjg9t/RtOpI83et7Mczitpj+Oo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738917462; c=relaxed/simple; bh=WZdQImwNoHHqSpy2Q3eqmp/iP94bs1fCIY64jXZD4/g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Tl1JAMYtbVqE6lpyxHGvcwpaeC5Jaa/UGcw0zSlTN0wJ+lSZ+zwHAGE5kR1XtLOiKWozTbMWQ7/DFV/gOzUmgJdC5vwM0UllTvxYrOT5nUJoaQY2hjjr5Oct1WQyMQ2Y0NTtSgXgT5bMGDO5pd8LigkUVfkeU4T+M7culCceVWU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b=c/7HcUIg; dkim=fail (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=rpZ5t3j6 reason="key not found in DNS"; arc=none smtp.client-ip=93.104.207.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="c/7HcUIg"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="rpZ5t3j6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1738917461; x=1770453461; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AFW0TtEuC1R227YTpxajrq5OhUhBVT+uUuYSWlEy4yY=; b=c/7HcUIgWMK5Wneci/9EZurSJe4m/bUaC+bb/jd4IgGV9g7gC1ChTndg YSdQ2qFVml4KctG0hyQVzWU25sJadcSj1f8b0FQcrFN5hS6vtQ7IGF+Ks GU9G7A0rJl9NdEPI6FU3wtUtSS+p38eRhGzHrb7HCcZt1DHRSEntEGJIh 8Lhc9+4K3OF+VvapwXNCqsDpAm6XzoN2sR5geORm/x29GOoNE9lOc0vsu +0lcdcZ8jXhz7u0KjqbjRhBz8IVFG9acGpCS4orqMUIo2vlLiuFZ3CLPQ oso+T2I5J0xrJnMDuS0tNN1zbrs9sbv/A9F4ip3ELycGE2W5HKCfE+Y6L Q==; X-CSE-ConnectionGUID: n0BqvstSTrWJTquL+npnKw== X-CSE-MsgGUID: gNk8fwG5SPW35iu3hrjoyg== X-IronPort-AV: E=Sophos;i="6.13,266,1732575600"; d="scan'208";a="41636120" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 07 Feb 2025 09:37:18 +0100 X-CheckPoint: {67A5C626-14-2D67083E-CAF60585} X-MAIL-CPID: 936AED959B21081A840AE6DDA0361249_0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C3599168346; Fri, 7 Feb 2025 09:37:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1738917433; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AFW0TtEuC1R227YTpxajrq5OhUhBVT+uUuYSWlEy4yY=; b=rpZ5t3j6zGVXzHvc5pVK36cwbQdd67GRr60fiDBrJBSz2RbVwYta741gGtgSDmcoe3tT0k qzI6wFbBqsn/Za+gwNiEPplEWOyrna3QS+zUnlrj+NCmO7PA3usGHROX8d+3XigvoHWwUT DxsIaYkCjDz2dEy2Bl93uEH0d00GNCzpsQCGA8Z7pv9uKdNsn5bxfHY14r61SB8wzR2usP zx0v7A9eed19LtAf6P3/WjHypnqQ9tV2tQzTMbv6w92MCnHgAoMWJbHTQ68FgYq+AiUqRx AZMm5cS1PzOP3Jp4px6a/e95aOZQJlKDCe7MnASkbSHG9KYqExF6Q7R2MDPNdA== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Srinivas Kandagatla Cc: Alexander Stein , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/10] arm64: dts: imx8mq: Add i.MX8M OCOTP disable fuse definitions Date: Fri, 7 Feb 2025 09:36:14 +0100 Message-Id: <20250207083616.1442887-10-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250207083616.1442887-1-alexander.stein@ew.tq-group.com> References: <20250207083616.1442887-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 These definitions define the location of corresponding disable bits in OCOTP peripheral. Signed-off-by: Alexander Stein Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq-ocotp.h | 37 ++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-ocotp.h diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h new file mode 100644 index 0000000000000..d991d57816264 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#ifndef __DTS_IMX8MQ_OCOTP_H +#define __DTS_IMX8MQ_OCOTP_H + +/* + * The OCOTP is a tuple of + * + */ + +#define IMX8MQ_OCOTP_M4_DISABLE 20 8 +#define IMX8MQ_OCOTP_M4_MPU_DISABLE 20 9 +#define IMX8MQ_OCOTP_M4_FPU_DISABLE 20 10 +#define IMX8MQ_OCOTP_USB_OTG1_DISABLE 20 11 +#define IMX8MQ_OCOTP_USB_OTG2_DISABLE 20 12 +#define IMX8MQ_OCOTP_DOLBY_DISABLE 20 13 +#define IMX8MQ_OCOTP_VP9_DISABLE 20 18 +#define IMX8MQ_OCOTP_HEVC_DISABLE 20 19 +#define IMX8MQ_OCOTP_AVC_DISABLE 20 20 +#define IMX8MQ_OCOTP_VPU_DISABLE 20 21 +#define IMX8MQ_OCOTP_PCIE1_DISABLE 20 22 +#define IMX8MQ_OCOTP_PCIE2_DISABLE 20 23 +#define IMX8MQ_OCOTP_GPU_DISABLE 20 24 +#define IMX8MQ_OCOTP_HDMI_DISABLE 20 25 +#define IMX8MQ_OCOTP_DC_DISABLE 20 26 +#define IMX8MQ_OCOTP_HDCP_DISABLE 20 27 +#define IMX8MQ_OCOTP_MIPI_DSI_DISABLE 20 28 +#define IMX8MQ_OCOTP_ENET_DISABLE 20 29 +#define IMX8MQ_OCOTP_MIPI_CSI1_DISABLE 20 30 +#define IMX8MQ_OCOTP_MIPI_CSI2_DISABLE 20 31 + +#endif /* __DTS_IMX8MQ_OCOTP_H */