| Message ID | 20250207083616.1442887-5-alexander.stein@ew.tq-group.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Make i.MX8M OCOTP work as accessing controller | expand |
On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote: >Mark ocotp as a access-controller and add references on peripherals >which can be disabled (fused). I am not sure whether gpcv2 changes should be included in this patchset or not. Just add access-controller for fused IP will not work. i.MX8M BLK-CTRL/GPC will hang if the related power domain is still touched by kernel. The pgc can't power up/down because clock is gated. This comment also apply to i.MX8MM/P. Regards Peng
Hi Peng, Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan: > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote: > >Mark ocotp as a access-controller and add references on peripherals > >which can be disabled (fused). > > I am not sure whether gpcv2 changes should be included in this patchset > or not. Just add access-controller for fused IP will not work. Well, I was able to successfully boot a i.MX8M Nano DualLite. > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still touched > by kernel. The pgc can't power up/down because clock is gated. Well, with GPU node disabled, no one should enable the power domain. But to be on the safe side I would also add access-controllers to the corresponding power domains as well. > This comment also apply to i.MX8MM/P. Sure. Do you have any information what is actually disabled by those fused? It seems it's the IP and their power domains. Anything else? Best regards, Alexander
> Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access- > controller references > > Hi Peng, > > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan: > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote: > > >Mark ocotp as a access-controller and add references on peripherals > > >which can be disabled (fused). > > > > I am not sure whether gpcv2 changes should be included in this > > patchset or not. Just add access-controller for fused IP will not work. > > Well, I was able to successfully boot a i.MX8M Nano DualLite. > > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still > > touched by kernel. The pgc can't power up/down because clock is > gated. > > Well, with GPU node disabled, no one should enable the power domain. > But to be on the safe side I would also add access-controllers to the > corresponding power domains as well. > > > This comment also apply to i.MX8MM/P. > > Sure. Do you have any information what is actually disabled by those > fused? > It seems it's the IP and their power domains. Anything else? In NXP downstream there is a patch for drivers/pmdomain/imx/imx8m-blk-ctrl.c soc: imx8m-blk-ctrl: Support fused modules For fused module, its pgc can't power up/down and clock is gated. Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put all power domains during suspend/resume. So we have to remove the pgc and clock of fused module from blk-ctrl DTS node. Update the driver to support such case. But this patch also needs U-Boot to update device tree nodes, I recalled that U-Boot will remove gpc nodes, but not update blk-ctrl nodes. Regards, Peng. > > Best regards, > Alexander > -- > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, > Germany Amtsgericht München, HRB 105018 > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2F > www.tq- > group.com%2F&data=05%7C02%7Cpeng.fan%40nxp.com%7Ca7392a7 > a9a7d480f69c108dd477447bc%7C686ea1d3bc2b4c6fa92cd99c5c301 > 635%7C0%7C0%7C638745286928288330%7CUnknown%7CTWFpbGZ > sb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW > 4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=F > R%2BeuYsheLUO8UY6sB%2FGFpTo2911r9tQDl%2BZFqnDqcY%3D&res > erved=0 > >
Am Montag, 10. Februar 2025, 03:36:48 CET schrieb Peng Fan: > ******************** > Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter. > Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it. > ******************** > > > Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access- > > controller references > > > > Hi Peng, > > > > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan: > > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote: > > > >Mark ocotp as a access-controller and add references on peripherals > > > >which can be disabled (fused). > > > > > > I am not sure whether gpcv2 changes should be included in this > > > patchset or not. Just add access-controller for fused IP will not work. > > > > Well, I was able to successfully boot a i.MX8M Nano DualLite. > > > > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still > > > touched by kernel. The pgc can't power up/down because clock is > > gated. > > > > Well, with GPU node disabled, no one should enable the power domain. > > But to be on the safe side I would also add access-controllers to the > > corresponding power domains as well. > > > > > This comment also apply to i.MX8MM/P. > > > > Sure. Do you have any information what is actually disabled by those > > fused? > > It seems it's the IP and their power domains. Anything else? > > In NXP downstream there is a patch for drivers/pmdomain/imx/imx8m-blk-ctrl.c > > soc: imx8m-blk-ctrl: Support fused modules > > For fused module, its pgc can't power up/down and clock is gated. > Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put > all power domains during suspend/resume. So we have to remove the > pgc and clock of fused module from blk-ctrl DTS node. > Update the driver to support such case. > > But this patch also needs U-Boot to update device tree nodes, > I recalled that U-Boot will remove gpc nodes, but not update blk-ctrl nodes. Does it work, if we add the access-controller as well for pgc_gpu3d on imx8mp? There is nothing in blk-ctrl AFAICS. But for VPU there is. Which clock needs to be removed there in case g1 is disabled? Best regards, Alexander
On Mon, Feb 10, 2025 at 04:48:56PM +0100, Alexander Stein wrote: >Am Montag, 10. Februar 2025, 03:36:48 CET schrieb Peng Fan: >> ******************** >> Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter. >> Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it. >> ******************** >> >> > Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access- >> > controller references >> > >> > Hi Peng, >> > >> > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan: >> > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote: >> > > >Mark ocotp as a access-controller and add references on peripherals >> > > >which can be disabled (fused). >> > > >> > > I am not sure whether gpcv2 changes should be included in this >> > > patchset or not. Just add access-controller for fused IP will not work. >> > >> > Well, I was able to successfully boot a i.MX8M Nano DualLite. >> > >> > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still >> > > touched by kernel. The pgc can't power up/down because clock is >> > gated. >> > >> > Well, with GPU node disabled, no one should enable the power domain. >> > But to be on the safe side I would also add access-controllers to the >> > corresponding power domains as well. >> > >> > > This comment also apply to i.MX8MM/P. >> > >> > Sure. Do you have any information what is actually disabled by those >> > fused? >> > It seems it's the IP and their power domains. Anything else? >> >> In NXP downstream there is a patch for drivers/pmdomain/imx/imx8m-blk-ctrl.c >> >> soc: imx8m-blk-ctrl: Support fused modules >> >> For fused module, its pgc can't power up/down and clock is gated. >> Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put >> all power domains during suspend/resume. So we have to remove the >> pgc and clock of fused module from blk-ctrl DTS node. >> Update the driver to support such case. >> >> But this patch also needs U-Boot to update device tree nodes, >> I recalled that U-Boot will remove gpc nodes, but not update blk-ctrl nodes. > >Does it work, if we add the access-controller as well for pgc_gpu3d >on imx8mp? There is nothing in blk-ctrl AFAICS. But for VPU there is. Adding access-controller under pgc_gpu node will not make fwdevlink work for the pgc_gpu nodes. It does not have compatible, and device is created by gpcv2 driver using platform_device_alloc. Same to vpu. >Which clock needs to be removed there in case g1 is disabled? Take i.MX8MP VC8000E as example, the vpumix blk ctrl, the vc8000e reference under vpumix blkctrl should be removed, including pd and clock. So for non-blkctrl nodes, it is fine to use access-controller and rely on fwdelink to defer probe. But for blk ctrl nodes, it will not work. For pgc nodes, it may or may not matter, not very sure for now. For blk ctrl nodes, we need provide a generic API saying access_control_check or directly using nvmem API. Regards, Peng > >Best regards, >Alexander >-- >TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany >Amtsgericht München, HRB 105018 >Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider >http://www.tq-group.com/ > >
Am Dienstag, 11. Februar 2025, 04:33:41 CET schrieb Peng Fan: > > On Mon, Feb 10, 2025 at 04:48:56PM +0100, Alexander Stein wrote: > >Am Montag, 10. Februar 2025, 03:36:48 CET schrieb Peng Fan: > >> > Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access- > >> > controller references > >> > > >> > Hi Peng, > >> > > >> > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan: > >> > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein wrote: > >> > > >Mark ocotp as a access-controller and add references on peripherals > >> > > >which can be disabled (fused). > >> > > > >> > > I am not sure whether gpcv2 changes should be included in this > >> > > patchset or not. Just add access-controller for fused IP will not work. > >> > > >> > Well, I was able to successfully boot a i.MX8M Nano DualLite. > >> > > >> > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is still > >> > > touched by kernel. The pgc can't power up/down because clock is > >> > gated. > >> > > >> > Well, with GPU node disabled, no one should enable the power domain. > >> > But to be on the safe side I would also add access-controllers to the > >> > corresponding power domains as well. > >> > > >> > > This comment also apply to i.MX8MM/P. > >> > > >> > Sure. Do you have any information what is actually disabled by those > >> > fused? > >> > It seems it's the IP and their power domains. Anything else? > >> > >> In NXP downstream there is a patch for drivers/pmdomain/imx/imx8m-blk-ctrl.c > >> > >> soc: imx8m-blk-ctrl: Support fused modules > >> > >> For fused module, its pgc can't power up/down and clock is gated. > >> Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put > >> all power domains during suspend/resume. So we have to remove the > >> pgc and clock of fused module from blk-ctrl DTS node. > >> Update the driver to support such case. > >> > >> But this patch also needs U-Boot to update device tree nodes, > >> I recalled that U-Boot will remove gpc nodes, but not update blk-ctrl nodes. > > > >Does it work, if we add the access-controller as well for pgc_gpu3d > >on imx8mp? There is nothing in blk-ctrl AFAICS. But for VPU there is. > > Adding access-controller under pgc_gpu node will not make fwdevlink > work for the pgc_gpu nodes. It does not have compatible, and device > is created by gpcv2 driver using platform_device_alloc. Same to vpu. > > >Which clock needs to be removed there in case g1 is disabled? > > Take i.MX8MP VC8000E as example, the vpumix blk ctrl, the vc8000e > reference under vpumix blkctrl should be removed, including pd and clock. Wait, so you want to remove the last entry from these properties? > clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, > <&clk IMX8MP_CLK_VPU_G2_ROOT>, > <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; > clock-names = "g1", "g2", "vc8000e"; This violates the DT binding. > So for non-blkctrl nodes, it is fine to use access-controller and rely > on fwdelink to defer probe. But for blk ctrl nodes, it will not work. > > For pgc nodes, it may or may not matter, not very sure for now. > > For blk ctrl nodes, we need provide a generic API saying > access_control_check or directly using nvmem API. Reading access-controllers.yaml this should still be feasible for providing the necessary information. But I'm note sure where to implement this. In e.g. imx-ocotp would be a very SoC-specific API. Best regards, Alexander
> Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access- > controller references > > Am Dienstag, 11. Februar 2025, 04:33:41 CET schrieb Peng Fan: > > > > On Mon, Feb 10, 2025 at 04:48:56PM +0100, Alexander Stein wrote: > > >Am Montag, 10. Februar 2025, 03:36:48 CET schrieb Peng Fan: > > >> > Subject: Re: [PATCH v2 04/10] arm64: dts: imx8mn: Add access- > > >> > controller references > > >> > > > >> > Hi Peng, > > >> > > > >> > Am Freitag, 7. Februar 2025, 13:02:13 CET schrieb Peng Fan: > > >> > > On Fri, Feb 07, 2025 at 09:36:09AM +0100, Alexander Stein > wrote: > > >> > > >Mark ocotp as a access-controller and add references on > > >> > > >peripherals which can be disabled (fused). > > >> > > > > >> > > I am not sure whether gpcv2 changes should be included in > this > > >> > > patchset or not. Just add access-controller for fused IP will not > work. > > >> > > > >> > Well, I was able to successfully boot a i.MX8M Nano DualLite. > > >> > > > >> > > i.MX8M BLK-CTRL/GPC will hang if the related power domain is > > >> > > still touched by kernel. The pgc can't power up/down because > > >> > > clock is > > >> > gated. > > >> > > > >> > Well, with GPU node disabled, no one should enable the power > domain. > > >> > But to be on the safe side I would also add access-controllers to > > >> > the corresponding power domains as well. > > >> > > > >> > > This comment also apply to i.MX8MM/P. > > >> > > > >> > Sure. Do you have any information what is actually disabled by > > >> > those fused? > > >> > It seems it's the IP and their power domains. Anything else? > > >> > > >> In NXP downstream there is a patch for > > >> drivers/pmdomain/imx/imx8m-blk-ctrl.c > > >> > > >> soc: imx8m-blk-ctrl: Support fused modules > > >> > > >> For fused module, its pgc can't power up/down and clock is > gated. > > >> Because imx8m-blk-ctrl driver will > pm_runtime_get_sync/pm_runtime_put > > >> all power domains during suspend/resume. So we have to > remove the > > >> pgc and clock of fused module from blk-ctrl DTS node. > > >> Update the driver to support such case. > > >> > > >> But this patch also needs U-Boot to update device tree nodes, I > > >> recalled that U-Boot will remove gpc nodes, but not update blk- > ctrl nodes. > > > > > >Does it work, if we add the access-controller as well for pgc_gpu3d > > >on imx8mp? There is nothing in blk-ctrl AFAICS. But for VPU there is. > > > > Adding access-controller under pgc_gpu node will not make > fwdevlink > > work for the pgc_gpu nodes. It does not have compatible, and device > is > > created by gpcv2 driver using platform_device_alloc. Same to vpu. > > > > >Which clock needs to be removed there in case g1 is disabled? > > > > Take i.MX8MP VC8000E as example, the vpumix blk ctrl, the vc8000e > > reference under vpumix blkctrl should be removed, including pd and > clock. > > Wait, so you want to remove the last entry from these properties? > > > clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, > > <&clk IMX8MP_CLK_VPU_G2_ROOT>, > > <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; > > clock-names = "g1", "g2", "vc8000e"; > > This violates the DT binding. Not sure whether dt bindings should be different for one SoC that some modules maybe fused out that not usable. Actually this is different SoC per my understanding. Without changing the binding, the idea I am thinking is to add nvmem = <&ocotp X>, <& ocotp Y>, xxxx; for the node. Then driver could check nvmem to see whether module avaibable. But for pgc, we still need the pd available from sw view, otherwise blk ctrl may not probe because of fwdevlink. Regards, Peng > > > So for non-blkctrl nodes, it is fine to use access-controller and rely > > on fwdelink to defer probe. But for blk ctrl nodes, it will not work. > > > > For pgc nodes, it may or may not matter, not very sure for now. > > > > For blk ctrl nodes, we need provide a generic API saying > > access_control_check or directly using nvmem API. > > Reading access-controllers.yaml this should still be feasible for > providing the necessary information. > But I'm note sure where to implement this. In e.g. imx-ocotp would be > a very SoC-specific API. > > Best regards, > Alexander > -- > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, > Germany Amtsgericht München, HRB 105018 > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2F > www.tq- > group.com%2F&data=05%7C02%7Cpeng.fan%40nxp.com%7Ccb387da > 6989845e6bee608dd4b3ccd2a%7C686ea1d3bc2b4c6fa92cd99c5c301 > 635%7C0%7C0%7C638749446703427130%7CUnknown%7CTWFpbGZ > sb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW > 4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=d > OARjpfOaGqV2GNJ9TPiUs7qd703QPOzjUiFFQMRX0s%3D&reserved=0 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a5f9cfb46e5dd..ee6c3a4be87fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> +#include "imx8mn-ocotp.h" #include "imx8mn-pinfunc.h" / { @@ -431,6 +432,7 @@ easrc: easrc@300c0000 { firmware-name = "imx/easrc/easrc-imx8mn.bin"; fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; + access-controllers = <&ocotp IMX8MN_OCOTP_ASRC_DISABLE>; status = "disabled"; }; }; @@ -571,6 +573,7 @@ ocotp: efuse@30350000 { clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <2>; /* * The register address below maps to the MX8M @@ -1053,6 +1056,7 @@ fec1: ethernet@30be0000 { nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; fsl,stop-mode = <&gpr 0x10 3>; + access-controllers = <&ocotp IMX8MN_OCOTP_ENET_DISABLE>; status = "disabled"; }; @@ -1091,6 +1095,7 @@ mipi_dsi: dsi@32e10000 { clock-names = "bus_clk", "sclk_mipi"; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; + access-controllers = <&ocotp IMX8MN_OCOTP_MIPI_DSI_DISABLE>; status = "disabled"; ports { @@ -1195,6 +1200,7 @@ mipi_csi: mipi-csi@32e30000 { <&clk IMX8MN_CLK_DISP_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + access-controllers = <&ocotp IMX8MN_OCOTP_MIPI_CSI_DISABLE>; status = "disabled"; ports { @@ -1225,6 +1231,7 @@ usbotg1: usb@32e40000 { phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; power-domains = <&pgc_hsiomix>; + access-controllers = <&ocotp IMX8MN_OCOTP_USB_OTG1_DISABLE>; status = "disabled"; }; @@ -1288,6 +1295,7 @@ gpu: gpu@38000000 { <400000000>, <1200000000>; power-domains = <&pgc_gpumix>; + access-controllers = <&ocotp IMX8MN_OCOTP_GPU3D_DISABLE>; }; gic: interrupt-controller@38800000 {
Mark ocotp as a access-controller and add references on peripherals which can be disabled (fused). Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)