@@ -11,6 +11,7 @@
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/thermal/thermal.h>
+#include "imx8mm-ocotp.h"
#include "imx8mm-pinfunc.h"
/ {
@@ -565,6 +566,7 @@ ocotp: efuse@30350000 {
/* For nvmem subnodes */
#address-cells = <1>;
#size-cells = <1>;
+ #access-controller-cells = <2>;
/*
* The register address below maps to the MX8M
@@ -1108,6 +1110,7 @@ fec1: ethernet@30be0000 {
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
fsl,stop-mode = <&gpr 0x10 3>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_ENET_DISABLE>;
status = "disabled";
};
@@ -1157,6 +1160,7 @@ mipi_dsi: dsi@32e10000 {
<&clk IMX8MM_CLK_24M>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_MIPI_DSI_DISABLE>;
status = "disabled";
ports {
@@ -1187,6 +1191,7 @@ csi: csi@32e20000 {
clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
clock-names = "mclk";
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_MIPI_CSI_DISABLE>;
status = "disabled";
port {
@@ -1270,6 +1275,7 @@ usbotg1: usb@32e40000 {
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_hsiomix>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_USB_OTG1_DISABLE>;
status = "disabled";
};
@@ -1290,6 +1296,7 @@ usbotg2: usb@32e50000 {
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
power-domains = <&pgc_hsiomix>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_USB_OTG2_DISABLE>;
status = "disabled";
};
@@ -1375,6 +1382,7 @@ pcie0: pcie@33800000 {
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
+ access-controllers = <&ocotp IMX8MM_OCOTP_PCIE1_DISABLE>;
status = "disabled";
};
@@ -1401,6 +1409,7 @@ pcie0_ep: pcie-ep@33800000 {
phy-names = "pcie-phy";
num-ib-windows = <4>;
num-ob-windows = <4>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_PCIE1_DISABLE>;
status = "disabled";
};
@@ -1418,6 +1427,7 @@ gpu_3d: gpu@38000000 {
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-rates = <0>, <800000000>;
power-domains = <&pgc_gpu>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_GPU3D_DISABLE>;
};
gpu_2d: gpu@38008000 {
@@ -1433,6 +1443,7 @@ gpu_2d: gpu@38008000 {
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-rates = <0>, <800000000>;
power-domains = <&pgc_gpu>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_GPU2D_DISABLE>;
};
vpu_g1: video-codec@38300000 {
@@ -1441,6 +1452,7 @@ vpu_g1: video-codec@38300000 {
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_G1_DISABLE>;
};
vpu_g2: video-codec@38310000 {
@@ -1449,6 +1461,7 @@ vpu_g2: video-codec@38310000 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
+ access-controllers = <&ocotp IMX8MM_OCOTP_G2_DISABLE>;
};
vpu_blk_ctrl: blk-ctrl@38330000 {
Mark ocotp as a access-controller and add references on peripherals which can be disabled (fused). Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)