| Message ID | 20250207163808.1208552-3-ciprianmarian.costea@oss.nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | add NXP RTC driver support for S32G2/S32G3 SoCs | expand |
On Fri, Feb 07, 2025 at 06:38:06PM +0200, Ciprian Costea wrote: > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > Add a RTC driver for NXP S32G2/S32G3 SoCs. > > RTC tracks clock time during system suspend. It can be a wakeup source > for the S32G2/S32G3 SoC based boards. > > The RTC module from S32G2/S32G3 is not battery-powered and it is not kept > alive during system reset. > > Co-developed-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> > Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> > Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> > Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > --- > drivers/rtc/Kconfig | 11 ++ > drivers/rtc/Makefile | 1 + > drivers/rtc/rtc-s32g.c | 383 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 395 insertions(+) > create mode 100644 drivers/rtc/rtc-s32g.c > > diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig > index 0bbbf778ecfa..510dc2db745d 100644 > --- a/drivers/rtc/Kconfig > +++ b/drivers/rtc/Kconfig > @@ -2103,4 +2103,15 @@ config RTC_DRV_AMLOGIC_A4 > This driver can also be built as a module. If so, the module > will be called "rtc-amlogic-a4". > > +config RTC_DRV_S32G > + tristate "RTC driver for S32G2/S32G3 SoCs" > + depends on ARCH_S32 || COMPILE_TEST > + depends on COMMON_CLK > + help > + Say yes to enable RTC driver for platforms based on the > + S32G2/S32G3 SoC family. > + > + This RTC module can be used as a wakeup source. > + Please note that it is not battery-powered. > + > endif # RTC_CLASS > diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile > index 489b4ab07068..e4b616ecd5ce 100644 > --- a/drivers/rtc/Makefile > +++ b/drivers/rtc/Makefile > @@ -161,6 +161,7 @@ obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o > obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o > obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o > obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o > +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o > obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o > obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o > obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o > diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c > new file mode 100644 > index 000000000000..3244b23c533e > --- /dev/null > +++ b/drivers/rtc/rtc-s32g.c ... > + > +static int s32g_rtc_suspend(struct device *dev) > +{ > + struct rtc_priv *priv = dev_get_drvdata(dev); > + u32 apival = readl(priv->rtc_base + APIVAL_OFFSET); > + > + /* RTC registers are being reset in suspend. > + * Thus store standby time. > + */ > + if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz), > + &priv->sleep_sec)) { > + dev_warn(dev, "Overflow on sleep cycles occurred. Resetting to 0.\n"); > + priv->sleep_sec = 0; > + } Strange. If RTC register are reset in suspend. How do it wake up system? Frank > + > + return 0; > +} > + > +static int s32g_rtc_resume(struct device *dev) > +{ > + struct rtc_priv *priv = dev_get_drvdata(dev); > + > + return rtc_clk_src_setup(priv); > +} > + > +static const struct of_device_id rtc_dt_ids[] = { > + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, > + { /* sentinel */ }, > +}; > + > +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, > + s32g_rtc_suspend, s32g_rtc_resume); > + > +static struct platform_driver s32g_rtc_driver = { > + .driver = { > + .name = "s32g-rtc", > + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), > + .of_match_table = rtc_dt_ids, > + }, > + .probe = s32g_rtc_probe, > +}; > +module_platform_driver(s32g_rtc_driver); > + > +MODULE_AUTHOR("NXP"); > +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); > +MODULE_LICENSE("GPL"); > -- > 2.45.2 >
On 2/7/2025 10:16 PM, Frank Li wrote: > On Fri, Feb 07, 2025 at 06:38:06PM +0200, Ciprian Costea wrote: >> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >> >> Add a RTC driver for NXP S32G2/S32G3 SoCs. >> >> RTC tracks clock time during system suspend. It can be a wakeup source >> for the S32G2/S32G3 SoC based boards. >> >> The RTC module from S32G2/S32G3 is not battery-powered and it is not kept >> alive during system reset. >> >> Co-developed-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> >> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> >> Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> >> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> >> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >> --- >> drivers/rtc/Kconfig | 11 ++ >> drivers/rtc/Makefile | 1 + >> drivers/rtc/rtc-s32g.c | 383 +++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 395 insertions(+) >> create mode 100644 drivers/rtc/rtc-s32g.c >> >> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig >> index 0bbbf778ecfa..510dc2db745d 100644 >> --- a/drivers/rtc/Kconfig >> +++ b/drivers/rtc/Kconfig >> @@ -2103,4 +2103,15 @@ config RTC_DRV_AMLOGIC_A4 >> This driver can also be built as a module. If so, the module >> will be called "rtc-amlogic-a4". >> >> +config RTC_DRV_S32G >> + tristate "RTC driver for S32G2/S32G3 SoCs" >> + depends on ARCH_S32 || COMPILE_TEST >> + depends on COMMON_CLK >> + help >> + Say yes to enable RTC driver for platforms based on the >> + S32G2/S32G3 SoC family. >> + >> + This RTC module can be used as a wakeup source. >> + Please note that it is not battery-powered. >> + >> endif # RTC_CLASS >> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile >> index 489b4ab07068..e4b616ecd5ce 100644 >> --- a/drivers/rtc/Makefile >> +++ b/drivers/rtc/Makefile >> @@ -161,6 +161,7 @@ obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o >> obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o >> obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o >> obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o >> +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o >> obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o >> obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o >> obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o >> diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c >> new file mode 100644 >> index 000000000000..3244b23c533e >> --- /dev/null >> +++ b/drivers/rtc/rtc-s32g.c > > ... > >> + >> +static int s32g_rtc_suspend(struct device *dev) >> +{ >> + struct rtc_priv *priv = dev_get_drvdata(dev); >> + u32 apival = readl(priv->rtc_base + APIVAL_OFFSET); >> + >> + /* RTC registers are being reset in suspend. >> + * Thus store standby time. >> + */ >> + if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz), >> + &priv->sleep_sec)) { >> + dev_warn(dev, "Overflow on sleep cycles occurred. Resetting to 0.\n"); >> + priv->sleep_sec = 0; >> + } > > Strange. If RTC register are reset in suspend. How do it wake up system? > > Frank > Hello Frank, I believe the transition between resume to run is a reset event. This would lead to the RTC registers being reset after resume from suspend (triggered via Suspend to RAM). On the other hand, the RTC is kept on during suspend for as long as its been set up (for example via rtcwake -s), thus waking up the sistem via an API interrupt. Regards, Ciprian >> + >> + return 0; >> +} >> + >> +static int s32g_rtc_resume(struct device *dev) >> +{ >> + struct rtc_priv *priv = dev_get_drvdata(dev); >> + >> + return rtc_clk_src_setup(priv); >> +} >> + >> +static const struct of_device_id rtc_dt_ids[] = { >> + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, >> + { /* sentinel */ }, >> +}; >> + >> +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, >> + s32g_rtc_suspend, s32g_rtc_resume); >> + >> +static struct platform_driver s32g_rtc_driver = { >> + .driver = { >> + .name = "s32g-rtc", >> + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), >> + .of_match_table = rtc_dt_ids, >> + }, >> + .probe = s32g_rtc_probe, >> +}; >> +module_platform_driver(s32g_rtc_driver); >> + >> +MODULE_AUTHOR("NXP"); >> +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); >> +MODULE_LICENSE("GPL"); >> -- >> 2.45.2 >>
On Tue, Feb 11, 2025 at 01:25:38PM +0200, Ciprian Marian Costea wrote: > On 2/7/2025 10:16 PM, Frank Li wrote: > > On Fri, Feb 07, 2025 at 06:38:06PM +0200, Ciprian Costea wrote: > > > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > > > > > Add a RTC driver for NXP S32G2/S32G3 SoCs. > > > > > > RTC tracks clock time during system suspend. It can be a wakeup source > > > for the S32G2/S32G3 SoC based boards. > > > > > > The RTC module from S32G2/S32G3 is not battery-powered and it is not kept > > > alive during system reset. > > > > > > Co-developed-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> > > > Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> > > > Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> > > > Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> > > > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > > --- > > > drivers/rtc/Kconfig | 11 ++ > > > drivers/rtc/Makefile | 1 + > > > drivers/rtc/rtc-s32g.c | 383 +++++++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 395 insertions(+) > > > create mode 100644 drivers/rtc/rtc-s32g.c > > > > > > diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig > > > index 0bbbf778ecfa..510dc2db745d 100644 > > > --- a/drivers/rtc/Kconfig > > > +++ b/drivers/rtc/Kconfig > > > @@ -2103,4 +2103,15 @@ config RTC_DRV_AMLOGIC_A4 > > > This driver can also be built as a module. If so, the module > > > will be called "rtc-amlogic-a4". > > > > > > +config RTC_DRV_S32G > > > + tristate "RTC driver for S32G2/S32G3 SoCs" > > > + depends on ARCH_S32 || COMPILE_TEST > > > + depends on COMMON_CLK > > > + help > > > + Say yes to enable RTC driver for platforms based on the > > > + S32G2/S32G3 SoC family. > > > + > > > + This RTC module can be used as a wakeup source. > > > + Please note that it is not battery-powered. > > > + > > > endif # RTC_CLASS > > > diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile > > > index 489b4ab07068..e4b616ecd5ce 100644 > > > --- a/drivers/rtc/Makefile > > > +++ b/drivers/rtc/Makefile > > > @@ -161,6 +161,7 @@ obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o > > > obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o > > > obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o > > > obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o > > > +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o > > > obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o > > > obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o > > > obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o > > > diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c > > > new file mode 100644 > > > index 000000000000..3244b23c533e > > > --- /dev/null > > > +++ b/drivers/rtc/rtc-s32g.c > > > > ... > > > > > + > > > +static int s32g_rtc_suspend(struct device *dev) > > > +{ > > > + struct rtc_priv *priv = dev_get_drvdata(dev); > > > + u32 apival = readl(priv->rtc_base + APIVAL_OFFSET); > > > + > > > + /* RTC registers are being reset in suspend. > > > + * Thus store standby time. > > > + */ > > > + if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz), > > > + &priv->sleep_sec)) { > > > + dev_warn(dev, "Overflow on sleep cycles occurred. Resetting to 0.\n"); > > > + priv->sleep_sec = 0; > > > + } > > > > Strange. If RTC register are reset in suspend. How do it wake up system? > > > > Frank > > > > Hello Frank, > > I believe the transition between resume to run is a reset event. This would > lead to the RTC registers being reset after resume from suspend (triggered > via Suspend to RAM). It is weird design. I suppose it should be design error. (any errata for it). Frank > > On the other hand, the RTC is kept on during suspend for as long as its been > set up (for example via rtcwake -s), thus waking up the sistem via an API > interrupt. > > Regards, > Ciprian > > > > + > > > + return 0; > > > +} > > > + > > > +static int s32g_rtc_resume(struct device *dev) > > > +{ > > > + struct rtc_priv *priv = dev_get_drvdata(dev); > > > + > > > + return rtc_clk_src_setup(priv); > > > +} > > > + > > > +static const struct of_device_id rtc_dt_ids[] = { > > > + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, > > > + { /* sentinel */ }, > > > +}; > > > + > > > +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, > > > + s32g_rtc_suspend, s32g_rtc_resume); > > > + > > > +static struct platform_driver s32g_rtc_driver = { > > > + .driver = { > > > + .name = "s32g-rtc", > > > + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), > > > + .of_match_table = rtc_dt_ids, > > > + }, > > > + .probe = s32g_rtc_probe, > > > +}; > > > +module_platform_driver(s32g_rtc_driver); > > > + > > > +MODULE_AUTHOR("NXP"); > > > +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); > > > +MODULE_LICENSE("GPL"); > > > -- > > > 2.45.2 > > > >
On 2/11/2025 7:07 PM, Frank Li wrote: > On Tue, Feb 11, 2025 at 01:25:38PM +0200, Ciprian Marian Costea wrote: >> On 2/7/2025 10:16 PM, Frank Li wrote: >>> On Fri, Feb 07, 2025 at 06:38:06PM +0200, Ciprian Costea wrote: >>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >>>> >>>> Add a RTC driver for NXP S32G2/S32G3 SoCs. >>>> >>>> RTC tracks clock time during system suspend. It can be a wakeup source >>>> for the S32G2/S32G3 SoC based boards. >>>> >>>> The RTC module from S32G2/S32G3 is not battery-powered and it is not kept >>>> alive during system reset. >>>> >>>> Co-developed-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> >>>> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> >>>> Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> >>>> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> >>>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >>>> --- >>>> drivers/rtc/Kconfig | 11 ++ >>>> drivers/rtc/Makefile | 1 + >>>> drivers/rtc/rtc-s32g.c | 383 +++++++++++++++++++++++++++++++++++++++++ >>>> 3 files changed, 395 insertions(+) >>>> create mode 100644 drivers/rtc/rtc-s32g.c >>>> >>>> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig >>>> index 0bbbf778ecfa..510dc2db745d 100644 >>>> --- a/drivers/rtc/Kconfig >>>> +++ b/drivers/rtc/Kconfig >>>> @@ -2103,4 +2103,15 @@ config RTC_DRV_AMLOGIC_A4 >>>> This driver can also be built as a module. If so, the module >>>> will be called "rtc-amlogic-a4". >>>> >>>> +config RTC_DRV_S32G >>>> + tristate "RTC driver for S32G2/S32G3 SoCs" >>>> + depends on ARCH_S32 || COMPILE_TEST >>>> + depends on COMMON_CLK >>>> + help >>>> + Say yes to enable RTC driver for platforms based on the >>>> + S32G2/S32G3 SoC family. >>>> + >>>> + This RTC module can be used as a wakeup source. >>>> + Please note that it is not battery-powered. >>>> + >>>> endif # RTC_CLASS >>>> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile >>>> index 489b4ab07068..e4b616ecd5ce 100644 >>>> --- a/drivers/rtc/Makefile >>>> +++ b/drivers/rtc/Makefile >>>> @@ -161,6 +161,7 @@ obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o >>>> obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o >>>> obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o >>>> obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o >>>> +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o >>>> obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o >>>> obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o >>>> obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o >>>> diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c >>>> new file mode 100644 >>>> index 000000000000..3244b23c533e >>>> --- /dev/null >>>> +++ b/drivers/rtc/rtc-s32g.c >>> >>> ... >>> >>>> + >>>> +static int s32g_rtc_suspend(struct device *dev) >>>> +{ >>>> + struct rtc_priv *priv = dev_get_drvdata(dev); >>>> + u32 apival = readl(priv->rtc_base + APIVAL_OFFSET); >>>> + >>>> + /* RTC registers are being reset in suspend. >>>> + * Thus store standby time. >>>> + */ >>>> + if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz), >>>> + &priv->sleep_sec)) { >>>> + dev_warn(dev, "Overflow on sleep cycles occurred. Resetting to 0.\n"); >>>> + priv->sleep_sec = 0; >>>> + } >>> >>> Strange. If RTC register are reset in suspend. How do it wake up system? >>> >>> Frank >>> >> >> Hello Frank, >> >> I believe the transition between resume to run is a reset event. This would >> lead to the RTC registers being reset after resume from suspend (triggered >> via Suspend to RAM). > > It is weird design. I suppose it should be design error. (any errata for > it). > > Frank > Unfortunately I could not find any such errata. But this behaviour (RTC registers being reset) is what I see when resuming from Suspend to RAM operations. Regards, Ciprian >> >> On the other hand, the RTC is kept on during suspend for as long as its been >> set up (for example via rtcwake -s), thus waking up the sistem via an API >> interrupt. >> >> Regards, >> Ciprian >> >>>> + >>>> + return 0; >>>> +} >>>> + >>>> +static int s32g_rtc_resume(struct device *dev) >>>> +{ >>>> + struct rtc_priv *priv = dev_get_drvdata(dev); >>>> + >>>> + return rtc_clk_src_setup(priv); >>>> +} >>>> + >>>> +static const struct of_device_id rtc_dt_ids[] = { >>>> + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, >>>> + { /* sentinel */ }, >>>> +}; >>>> + >>>> +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, >>>> + s32g_rtc_suspend, s32g_rtc_resume); >>>> + >>>> +static struct platform_driver s32g_rtc_driver = { >>>> + .driver = { >>>> + .name = "s32g-rtc", >>>> + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), >>>> + .of_match_table = rtc_dt_ids, >>>> + }, >>>> + .probe = s32g_rtc_probe, >>>> +}; >>>> +module_platform_driver(s32g_rtc_driver); >>>> + >>>> +MODULE_AUTHOR("NXP"); >>>> +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); >>>> +MODULE_LICENSE("GPL"); >>>> -- >>>> 2.45.2 >>>> >>
On Wed, Feb 12, 2025 at 10:11:35AM +0200, Ciprian Marian Costea wrote: > On 2/11/2025 7:07 PM, Frank Li wrote: > > On Tue, Feb 11, 2025 at 01:25:38PM +0200, Ciprian Marian Costea wrote: > > > On 2/7/2025 10:16 PM, Frank Li wrote: > > > > On Fri, Feb 07, 2025 at 06:38:06PM +0200, Ciprian Costea wrote: > > > > > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > > > > > > > > > Add a RTC driver for NXP S32G2/S32G3 SoCs. > > > > > > > > > > RTC tracks clock time during system suspend. It can be a wakeup source > > > > > for the S32G2/S32G3 SoC based boards. > > > > > > > > > > The RTC module from S32G2/S32G3 is not battery-powered and it is not kept > > > > > alive during system reset. > > > > > > > > > > Co-developed-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> > > > > > Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> > > > > > Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> > > > > > Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> > > > > > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > > > > --- > > > > > drivers/rtc/Kconfig | 11 ++ > > > > > drivers/rtc/Makefile | 1 + > > > > > drivers/rtc/rtc-s32g.c | 383 +++++++++++++++++++++++++++++++++++++++++ > > > > > 3 files changed, 395 insertions(+) > > > > > create mode 100644 drivers/rtc/rtc-s32g.c > > > > > > > > > > diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig > > > > > index 0bbbf778ecfa..510dc2db745d 100644 > > > > > --- a/drivers/rtc/Kconfig > > > > > +++ b/drivers/rtc/Kconfig > > > > > @@ -2103,4 +2103,15 @@ config RTC_DRV_AMLOGIC_A4 > > > > > This driver can also be built as a module. If so, the module > > > > > will be called "rtc-amlogic-a4". > > > > > > > > > > +config RTC_DRV_S32G > > > > > + tristate "RTC driver for S32G2/S32G3 SoCs" > > > > > + depends on ARCH_S32 || COMPILE_TEST > > > > > + depends on COMMON_CLK > > > > > + help > > > > > + Say yes to enable RTC driver for platforms based on the > > > > > + S32G2/S32G3 SoC family. > > > > > + > > > > > + This RTC module can be used as a wakeup source. > > > > > + Please note that it is not battery-powered. > > > > > + > > > > > endif # RTC_CLASS > > > > > diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile > > > > > index 489b4ab07068..e4b616ecd5ce 100644 > > > > > --- a/drivers/rtc/Makefile > > > > > +++ b/drivers/rtc/Makefile > > > > > @@ -161,6 +161,7 @@ obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o > > > > > obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o > > > > > obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o > > > > > obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o > > > > > +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o > > > > > obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o > > > > > obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o > > > > > obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o > > > > > diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c > > > > > new file mode 100644 > > > > > index 000000000000..3244b23c533e > > > > > --- /dev/null > > > > > +++ b/drivers/rtc/rtc-s32g.c > > > > > > > > ... > > > > > > > > > + > > > > > +static int s32g_rtc_suspend(struct device *dev) > > > > > +{ > > > > > + struct rtc_priv *priv = dev_get_drvdata(dev); > > > > > + u32 apival = readl(priv->rtc_base + APIVAL_OFFSET); > > > > > + > > > > > + /* RTC registers are being reset in suspend. > > > > > + * Thus store standby time. > > > > > + */ > > > > > + if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz), > > > > > + &priv->sleep_sec)) { > > > > > + dev_warn(dev, "Overflow on sleep cycles occurred. Resetting to 0.\n"); > > > > > + priv->sleep_sec = 0; > > > > > + } > > > > > > > > Strange. If RTC register are reset in suspend. How do it wake up system? > > > > > > > > Frank > > > > > > > > > > Hello Frank, > > > > > > I believe the transition between resume to run is a reset event. This would > > > lead to the RTC registers being reset after resume from suspend (triggered > > > via Suspend to RAM). > > > > It is weird design. I suppose it should be design error. (any errata for > > it). > > > > Frank > > > > Unfortunately I could not find any such errata. But this behaviour (RTC > registers being reset) is what I see when resuming from Suspend to RAM > operations. Okay, it worth add comment here to descript hardware behaviour, which is actually uncommon. Frank > > Regards, > Ciprian > > > > > > > On the other hand, the RTC is kept on during suspend for as long as its been > > > set up (for example via rtcwake -s), thus waking up the sistem via an API > > > interrupt. > > > > > > Regards, > > > Ciprian > > > > > > > > + > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int s32g_rtc_resume(struct device *dev) > > > > > +{ > > > > > + struct rtc_priv *priv = dev_get_drvdata(dev); > > > > > + > > > > > + return rtc_clk_src_setup(priv); > > > > > +} > > > > > + > > > > > +static const struct of_device_id rtc_dt_ids[] = { > > > > > + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, > > > > > + { /* sentinel */ }, > > > > > +}; > > > > > + > > > > > +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, > > > > > + s32g_rtc_suspend, s32g_rtc_resume); > > > > > + > > > > > +static struct platform_driver s32g_rtc_driver = { > > > > > + .driver = { > > > > > + .name = "s32g-rtc", > > > > > + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), > > > > > + .of_match_table = rtc_dt_ids, > > > > > + }, > > > > > + .probe = s32g_rtc_probe, > > > > > +}; > > > > > +module_platform_driver(s32g_rtc_driver); > > > > > + > > > > > +MODULE_AUTHOR("NXP"); > > > > > +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); > > > > > +MODULE_LICENSE("GPL"); > > > > > -- > > > > > 2.45.2 > > > > > > > > >
On 2/12/2025 5:50 PM, Frank Li wrote: > On Wed, Feb 12, 2025 at 10:11:35AM +0200, Ciprian Marian Costea wrote: >> On 2/11/2025 7:07 PM, Frank Li wrote: >>> On Tue, Feb 11, 2025 at 01:25:38PM +0200, Ciprian Marian Costea wrote: >>>> On 2/7/2025 10:16 PM, Frank Li wrote: >>>>> On Fri, Feb 07, 2025 at 06:38:06PM +0200, Ciprian Costea wrote: >>>>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >>>>>> >>>>>> Add a RTC driver for NXP S32G2/S32G3 SoCs. >>>>>> >>>>>> RTC tracks clock time during system suspend. It can be a wakeup source >>>>>> for the S32G2/S32G3 SoC based boards. >>>>>> >>>>>> The RTC module from S32G2/S32G3 is not battery-powered and it is not kept >>>>>> alive during system reset. >>>>>> >>>>>> Co-developed-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> >>>>>> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> >>>>>> Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> >>>>>> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> >>>>>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >>>>>> --- >>>>>> drivers/rtc/Kconfig | 11 ++ >>>>>> drivers/rtc/Makefile | 1 + >>>>>> drivers/rtc/rtc-s32g.c | 383 +++++++++++++++++++++++++++++++++++++++++ >>>>>> 3 files changed, 395 insertions(+) >>>>>> create mode 100644 drivers/rtc/rtc-s32g.c >>>>>> >>>>>> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig >>>>>> index 0bbbf778ecfa..510dc2db745d 100644 >>>>>> --- a/drivers/rtc/Kconfig >>>>>> +++ b/drivers/rtc/Kconfig >>>>>> @@ -2103,4 +2103,15 @@ config RTC_DRV_AMLOGIC_A4 >>>>>> This driver can also be built as a module. If so, the module >>>>>> will be called "rtc-amlogic-a4". >>>>>> >>>>>> +config RTC_DRV_S32G >>>>>> + tristate "RTC driver for S32G2/S32G3 SoCs" >>>>>> + depends on ARCH_S32 || COMPILE_TEST >>>>>> + depends on COMMON_CLK >>>>>> + help >>>>>> + Say yes to enable RTC driver for platforms based on the >>>>>> + S32G2/S32G3 SoC family. >>>>>> + >>>>>> + This RTC module can be used as a wakeup source. >>>>>> + Please note that it is not battery-powered. >>>>>> + >>>>>> endif # RTC_CLASS >>>>>> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile >>>>>> index 489b4ab07068..e4b616ecd5ce 100644 >>>>>> --- a/drivers/rtc/Makefile >>>>>> +++ b/drivers/rtc/Makefile >>>>>> @@ -161,6 +161,7 @@ obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o >>>>>> obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o >>>>>> obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o >>>>>> obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o >>>>>> +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o >>>>>> obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o >>>>>> obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o >>>>>> obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o >>>>>> diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c >>>>>> new file mode 100644 >>>>>> index 000000000000..3244b23c533e >>>>>> --- /dev/null >>>>>> +++ b/drivers/rtc/rtc-s32g.c >>>>> >>>>> ... >>>>> >>>>>> + >>>>>> +static int s32g_rtc_suspend(struct device *dev) >>>>>> +{ >>>>>> + struct rtc_priv *priv = dev_get_drvdata(dev); >>>>>> + u32 apival = readl(priv->rtc_base + APIVAL_OFFSET); >>>>>> + >>>>>> + /* RTC registers are being reset in suspend. >>>>>> + * Thus store standby time. >>>>>> + */ >>>>>> + if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz), >>>>>> + &priv->sleep_sec)) { >>>>>> + dev_warn(dev, "Overflow on sleep cycles occurred. Resetting to 0.\n"); >>>>>> + priv->sleep_sec = 0; >>>>>> + } >>>>> >>>>> Strange. If RTC register are reset in suspend. How do it wake up system? >>>>> >>>>> Frank >>>>> >>>> >>>> Hello Frank, >>>> >>>> I believe the transition between resume to run is a reset event. This would >>>> lead to the RTC registers being reset after resume from suspend (triggered >>>> via Suspend to RAM). >>> >>> It is weird design. I suppose it should be design error. (any errata for >>> it). >>> >>> Frank >>> >> >> Unfortunately I could not find any such errata. But this behaviour (RTC >> registers being reset) is what I see when resuming from Suspend to RAM >> operations. > > Okay, it worth add comment here to descript hardware behaviour, which is > actually uncommon. > > Frank > Sure. I will add such description on the resume path in V8. Regards, Ciprian >> >> Regards, >> Ciprian >> >>>> >>>> On the other hand, the RTC is kept on during suspend for as long as its been >>>> set up (for example via rtcwake -s), thus waking up the sistem via an API >>>> interrupt. >>>> >>>> Regards, >>>> Ciprian >>>> >>>>>> + >>>>>> + return 0; >>>>>> +} >>>>>> + >>>>>> +static int s32g_rtc_resume(struct device *dev) >>>>>> +{ >>>>>> + struct rtc_priv *priv = dev_get_drvdata(dev); >>>>>> + >>>>>> + return rtc_clk_src_setup(priv); >>>>>> +} >>>>>> + >>>>>> +static const struct of_device_id rtc_dt_ids[] = { >>>>>> + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, >>>>>> + { /* sentinel */ }, >>>>>> +}; >>>>>> + >>>>>> +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, >>>>>> + s32g_rtc_suspend, s32g_rtc_resume); >>>>>> + >>>>>> +static struct platform_driver s32g_rtc_driver = { >>>>>> + .driver = { >>>>>> + .name = "s32g-rtc", >>>>>> + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), >>>>>> + .of_match_table = rtc_dt_ids, >>>>>> + }, >>>>>> + .probe = s32g_rtc_probe, >>>>>> +}; >>>>>> +module_platform_driver(s32g_rtc_driver); >>>>>> + >>>>>> +MODULE_AUTHOR("NXP"); >>>>>> +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); >>>>>> +MODULE_LICENSE("GPL"); >>>>>> -- >>>>>> 2.45.2 >>>>>> >>>> >>
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 0bbbf778ecfa..510dc2db745d 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -2103,4 +2103,15 @@ config RTC_DRV_AMLOGIC_A4 This driver can also be built as a module. If so, the module will be called "rtc-amlogic-a4". +config RTC_DRV_S32G + tristate "RTC driver for S32G2/S32G3 SoCs" + depends on ARCH_S32 || COMPILE_TEST + depends on COMMON_CLK + help + Say yes to enable RTC driver for platforms based on the + S32G2/S32G3 SoC family. + + This RTC module can be used as a wakeup source. + Please note that it is not battery-powered. + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 489b4ab07068..e4b616ecd5ce 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -161,6 +161,7 @@ obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c new file mode 100644 index 000000000000..3244b23c533e --- /dev/null +++ b/drivers/rtc/rtc-s32g.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2025 NXP + */ + +#include <linux/clk.h> +#include <linux/iopoll.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/rtc.h> + +#define RTCC_OFFSET 0x4ul +#define RTCS_OFFSET 0x8ul +#define APIVAL_OFFSET 0x10ul + +/* RTCC fields */ +#define RTCC_CNTEN BIT(31) +#define RTCC_APIEN BIT(15) +#define RTCC_APIIE BIT(14) +#define RTCC_CLKSEL_MASK GENMASK(13, 12) +#define RTCC_DIV512EN BIT(11) +#define RTCC_DIV32EN BIT(10) + +/* RTCS fields */ +#define RTCS_INV_API BIT(17) +#define RTCS_APIF BIT(13) + +#define APIVAL_MAX_VAL GENMASK(31, 0) +#define RTC_SYNCH_TIMEOUT (100 * USEC_PER_MSEC) + +/* + * S32G2 and S32G3 SoCs have RTC clock source1 reserved and + * should not be used. + */ +#define RTC_CLK_SRC1_RESERVED BIT(1) + +/* + * S32G RTC module has a 512 value and a 32 value hardware frequency + * divisors (DIV512 and DIV32) which could be used to achieve higher + * counter ranges by lowering the RTC frequency. + */ +enum { + DIV1 = 1, + DIV32 = 32, + DIV512 = 512, + DIV512_32 = 16384 +}; + +static const char *const rtc_clk_src[] = { + "source0", + "source1", + "source2", + "source3" +}; + +struct rtc_priv { + struct rtc_device *rdev; + void __iomem *rtc_base; + struct clk *ipg; + struct clk *clk_src; + const struct rtc_soc_data *rtc_data; + u64 rtc_hz; + time64_t sleep_sec; + int irq; + u32 clk_src_idx; +}; + +struct rtc_soc_data { + u32 clk_div; + u32 reserved_clk_mask; +}; + +static const struct rtc_soc_data rtc_s32g2_data = { + .clk_div = DIV512_32, + .reserved_clk_mask = RTC_CLK_SRC1_RESERVED, +}; + +static irqreturn_t s32g_rtc_handler(int irq, void *dev) +{ + struct rtc_priv *priv = platform_get_drvdata(dev); + u32 status; + + status = readl(priv->rtc_base + RTCS_OFFSET); + + if (status & RTCS_APIF) { + writel(0x0, priv->rtc_base + APIVAL_OFFSET); + writel(status | RTCS_APIF, priv->rtc_base + RTCS_OFFSET); + } + + rtc_update_irq(priv->rdev, 1, RTC_IRQF | RTC_AF); + + return IRQ_HANDLED; +} + +/* + * The function is not really getting time from the RTC since the S32G RTC + * has several limitations. Thus, to setup alarm use system time. + */ +static int s32g_rtc_read_time(struct device *dev, + struct rtc_time *tm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + time64_t sec; + + if (check_add_overflow(ktime_get_real_seconds(), + priv->sleep_sec, &sec)) + return -ERANGE; + + rtc_time64_to_tm(sec, tm); + + return 0; +} + +static int s32g_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 rtcc, rtcs; + + rtcc = readl(priv->rtc_base + RTCC_OFFSET); + rtcs = readl(priv->rtc_base + RTCS_OFFSET); + + alrm->enabled = rtcc & RTCC_APIIE; + if (alrm->enabled) + alrm->pending = !(rtcs & RTCS_APIF); + + return 0; +} + +static int s32g_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 rtcc; + + /* RTC API functionality is used both for triggering interrupts + * and as a wakeup event. Hence it should always be enabled. + */ + rtcc = readl(priv->rtc_base + RTCC_OFFSET); + rtcc |= RTCC_APIEN | RTCC_APIIE; + writel(rtcc, priv->rtc_base + RTCC_OFFSET); + + return 0; +} + +static int s32g_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + unsigned long long cycles; + long long t_offset; + time64_t alrm_time; + u32 rtcs; + int ret; + + alrm_time = rtc_tm_to_time64(&alrm->time); + t_offset = alrm_time - ktime_get_real_seconds() - priv->sleep_sec; + if (t_offset < 0) + return -ERANGE; + + cycles = t_offset * priv->rtc_hz; + if (cycles > APIVAL_MAX_VAL) + return -ERANGE; + + /* APIVAL could have been reset from the IRQ handler. + * Hence, we wait in case there is a synchronization process. + */ + ret = read_poll_timeout(readl, rtcs, !(rtcs & RTCS_INV_API), + 0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET); + if (ret) + return ret; + + writel(cycles, priv->rtc_base + APIVAL_OFFSET); + + return read_poll_timeout(readl, rtcs, !(rtcs & RTCS_INV_API), + 0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET); +} + +/* + * Disable the 32-bit free running counter. + * This allows Clock Source and Divisors selection + * to be performed without causing synchronization issues. + */ +static void s32g_rtc_disable(struct rtc_priv *priv) +{ + u32 rtcc = readl(priv->rtc_base + RTCC_OFFSET); + + rtcc &= ~RTCC_CNTEN; + writel(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static void s32g_rtc_enable(struct rtc_priv *priv) +{ + u32 rtcc = readl(priv->rtc_base + RTCC_OFFSET); + + rtcc |= RTCC_CNTEN; + writel(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static int rtc_clk_src_setup(struct rtc_priv *priv) +{ + u32 rtcc; + + if (priv->rtc_data->reserved_clk_mask & (1 << priv->clk_src_idx)) + return -EOPNOTSUPP; + + rtcc = FIELD_PREP(RTCC_CLKSEL_MASK, priv->clk_src_idx); + + switch (priv->rtc_data->clk_div) { + case DIV512_32: + rtcc |= RTCC_DIV512EN; + rtcc |= RTCC_DIV32EN; + break; + case DIV512: + rtcc |= RTCC_DIV512EN; + break; + case DIV32: + rtcc |= RTCC_DIV32EN; + break; + case DIV1: + break; + default: + return -EINVAL; + } + + rtcc |= RTCC_APIEN | RTCC_APIIE; + /* + * Make sure the CNTEN is 0 before we configure + * the clock source and dividers. + */ + s32g_rtc_disable(priv); + writel(rtcc, priv->rtc_base + RTCC_OFFSET); + s32g_rtc_enable(priv); + + return 0; +} + +static const struct rtc_class_ops rtc_ops = { + .read_time = s32g_rtc_read_time, + .read_alarm = s32g_rtc_read_alarm, + .set_alarm = s32g_rtc_set_alarm, + .alarm_irq_enable = s32g_rtc_alarm_irq_enable, +}; + +static int rtc_clk_dts_setup(struct rtc_priv *priv, + struct device *dev) +{ + u32 i; + + priv->ipg = devm_clk_get_enabled(dev, "ipg"); + if (IS_ERR(priv->ipg)) + return dev_err_probe(dev, PTR_ERR(priv->ipg), + "Failed to get 'ipg' clock\n"); + + for (i = 0; i < ARRAY_SIZE(rtc_clk_src); i++) { + priv->clk_src = devm_clk_get_enabled(dev, rtc_clk_src[i]); + if (!IS_ERR(priv->clk_src)) { + priv->clk_src_idx = i; + break; + } + } + + if (IS_ERR(priv->clk_src)) + return dev_err_probe(dev, PTR_ERR(priv->clk_src), + "Failed to get rtc module clock source\n"); + + return 0; +} + +static int s32g_rtc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtc_priv *priv; + unsigned long rtc_hz; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->rtc_data = of_device_get_match_data(dev); + if (!priv->rtc_data) + return -ENODEV; + + priv->rtc_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->rtc_base)) + return PTR_ERR(priv->rtc_base); + + device_init_wakeup(dev, true); + + ret = rtc_clk_dts_setup(priv, dev); + if (ret) + return ret; + + priv->rdev = devm_rtc_allocate_device(dev); + if (IS_ERR(priv->rdev)) + return PTR_ERR(priv->rdev); + + ret = rtc_clk_src_setup(priv); + if (ret) + return ret; + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) { + ret = priv->irq; + goto disable_rtc; + } + + rtc_hz = clk_get_rate(priv->clk_src); + if (!rtc_hz) { + dev_err(dev, "Failed to get RTC frequency\n"); + ret = -EINVAL; + goto disable_rtc; + } + + priv->rtc_hz = rtc_hz / priv->rtc_data->clk_div; + if (rtc_hz % priv->rtc_data->clk_div) + priv->rtc_hz++; + + platform_set_drvdata(pdev, priv); + priv->rdev->ops = &rtc_ops; + + ret = devm_request_irq(dev, priv->irq, + s32g_rtc_handler, 0, dev_name(dev), pdev); + if (ret) { + dev_err(dev, "Request interrupt %d failed, error: %d\n", + priv->irq, ret); + goto disable_rtc; + } + + ret = devm_rtc_register_device(priv->rdev); + if (ret) + goto disable_rtc; + + return 0; + +disable_rtc: + s32g_rtc_disable(priv); + return ret; +} + +static int s32g_rtc_suspend(struct device *dev) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 apival = readl(priv->rtc_base + APIVAL_OFFSET); + + /* RTC registers are being reset in suspend. + * Thus store standby time. + */ + if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz), + &priv->sleep_sec)) { + dev_warn(dev, "Overflow on sleep cycles occurred. Resetting to 0.\n"); + priv->sleep_sec = 0; + } + + return 0; +} + +static int s32g_rtc_resume(struct device *dev) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + + return rtc_clk_src_setup(priv); +} + +static const struct of_device_id rtc_dt_ids[] = { + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, + { /* sentinel */ }, +}; + +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, + s32g_rtc_suspend, s32g_rtc_resume); + +static struct platform_driver s32g_rtc_driver = { + .driver = { + .name = "s32g-rtc", + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), + .of_match_table = rtc_dt_ids, + }, + .probe = s32g_rtc_probe, +}; +module_platform_driver(s32g_rtc_driver); + +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); +MODULE_LICENSE("GPL");