From patchwork Thu Feb 27 16:58:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994932 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C64C1DCB09 for ; Thu, 27 Feb 2025 17:00:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675658; cv=none; b=flORGizR0EcDDyJ+43cEMhmA2NxgAed4nrV/fyN9j6y0OijOCWQsszopmwpW5IwmJOCYei0UgEjtCi4NkT8/dT16KYCANeYlcPPwVnmcfNzxmOMPVE3ph7uqrQreikSm686Tz4pZq/+qrIgcjTj9+as8Si0s3iZl0yrgXY1kT4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675658; c=relaxed/simple; bh=Wb7l2NxkfTb4lFzMz+B7+c0N20iip7NoPTO771zlIEY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dXlnMzoiAxXF8kv8HTv7DVZKEIeZWj5oxecqKUQ4PRQ+fulzCCt3EAUZRV4SUMRxPycGjrFL+Luk3zs15tMAEIiJI9SNGWo5Q/nwQsYQCIboInbVQcPSLgxqZ0L8+HngHTNpdbpCEk9a0jxZ6LiKcqJ3v6GgUMkRr6Cz8BYXVzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=LbbTlbjw; arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="LbbTlbjw" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5215110382F20; Thu, 27 Feb 2025 18:00:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1740675648; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rBr0cQee0ICtEgGCoLJb0hDKj8AQwhHIxt049wAgmYA=; b=LbbTlbjwQbsg6PEnktAyQeVoYU26GGNb16ZmQXDCe6pl4IpTdNp2N2HM0+vc6riTm6O9Tu grDd/Cn/6jEVDpbgY++QH4Pdg1xtgHz71iD8+HzFoyuzGhRBBrHgZtoYxyP74MotFWV/TI LbhZdNPYPKbqXDVkDc5BzpAv7BANHjTrGwKuxx6YavDfl+69SkZJW6oT/X8i+IZGW7XPEx NHBGiKX6hbcQSttm/DLwNfIT60VtkLBCZH9RPN33HtezfL7nhbuMLH5seRJB/xxstQTUx5 TiLo8INRhoSlLsWqPt3w1MVBBou/rGRr8APk2inl1qqezMiMzZ1HIi0RlhVaZA== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 3/9] dt-bindings: gpu: mali-valhall-csf: Document optional reset Date: Thu, 27 Feb 2025 17:58:03 +0100 Message-ID: <20250227170012.124768-4-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Document support for one optional reset. Signed-off-by: Marek Vasut Reviewed-by: Frank Li Acked-by: Rob Herring (Arm) --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index a5b4e00217587..0efa06822a543 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -61,6 +61,9 @@ properties: minItems: 1 maxItems: 5 + resets: + maxItems: 1 + sram-supply: true "#cooling-cells":