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[v6,00/20] ICELAKE DSI DRIVER

Message ID 1537095223-5184-1-git-send-email-madhav.chauhan@intel.com (mailing list archive)
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Series ICELAKE DSI DRIVER | expand

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Chauhan, Madhav Sept. 16, 2018, 10:53 a.m. UTC
From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
GPU/Display Engine and same could be extended for future Intel platforms as well.
DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.

So, a new DSI driver has been added inside I915.

Given below patches are the part of new DSI driver which implements BSPEC
sequence till panel programming. Rest of the patches will be published
to GITHUB.

v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some
other few patches.
v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
    Ville. Also addressed review comments for couple of patches.
v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes.
v5: Rebase on drm-tip after initial 7 patches got merged.
v6: Addressed various review comments from Jani N, Ville, Vandita.

Madhav Chauhan (20):
  drm/i915/icl: Configure lane sequencing of combo phy transmitter
  drm/i915/icl: DSI vswing programming sequence
  drm/i915/icl: Enable DDI Buffer
  drm/i915/icl: Program T_INIT_MASTER registers
  drm/i915/icl: Define data/clock lanes dphy timing registers
  drm/i915/icl: Program DSI clock and data lane timing params
  drm/i915/icl: Define TA_TIMING_PARAM registers
  drm/i915/icl: Program TA_TIMING_PARAM registers
  drm/i915/icl: Get DSI transcoder for a given port
  drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  drm/i915/icl: Configure DSI transcoders
  drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
  drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
  drm/i915/icl: Define DSI transcoder timing registers
  drm/i915/icl: Configure DSI transcoder timings
  drm/i915/icl: Define TRANS_CONF register for DSI
  drm/i915/icl: Enable DSI transcoders
  drm/i915/icl: Define DSI panel programming registers
  drm/i915/icl: Set max return packet size for DSI panel

 drivers/gpu/drm/i915/i915_pci.c      |   6 +-
 drivers/gpu/drm/i915/i915_reg.h      | 208 +++++++++++++
 drivers/gpu/drm/i915/icl_dsi.c       | 567 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.h |   6 +-
 drivers/gpu/drm/i915/intel_dsi.h     |   7 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 202 +++++++++----
 6 files changed, 934 insertions(+), 62 deletions(-)