From patchwork Sun Sep 16 10:53:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chauhan, Madhav" X-Patchwork-Id: 10601829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A794114DB for ; Sun, 16 Sep 2018 17:47:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B97E9201BC for ; Sun, 16 Sep 2018 17:47:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ABE4228471; Sun, 16 Sep 2018 17:47:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 564E7201BC for ; Sun, 16 Sep 2018 17:47:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F22DD6E2C0; Sun, 16 Sep 2018 17:44:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24B8F6E007 for ; Sun, 16 Sep 2018 11:03:58 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Sep 2018 04:03:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,381,1531810800"; d="scan'208,223";a="74701202" Received: from madhav-desktop.iind.intel.com ([10.223.25.13]) by orsmga006.jf.intel.com with ESMTP; 16 Sep 2018 04:03:55 -0700 From: Madhav Chauhan To: intel-gfx@lists.freedesktop.org Date: Sun, 16 Sep 2018 16:23:23 +0530 Message-Id: <1537095223-5184-1-git-send-email-madhav.chauhan@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH v6 00/20] ICELAKE DSI DRIVER X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, komala.b.rangappa@intel.com, rodrigo.vivi@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to GPU/Display Engine and same could be extended for future Intel platforms as well. DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification. So, a new DSI driver has been added inside I915. Given below patches are the part of new DSI driver which implements BSPEC sequence till panel programming. Rest of the patches will be published to GITHUB. v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some other few patches. v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel, Ville. Also addressed review comments for couple of patches. v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes. v5: Rebase on drm-tip after initial 7 patches got merged. v6: Addressed various review comments from Jani N, Ville, Vandita. Madhav Chauhan (20): drm/i915/icl: Configure lane sequencing of combo phy transmitter drm/i915/icl: DSI vswing programming sequence drm/i915/icl: Enable DDI Buffer drm/i915/icl: Program T_INIT_MASTER registers drm/i915/icl: Define data/clock lanes dphy timing registers drm/i915/icl: Program DSI clock and data lane timing params drm/i915/icl: Define TA_TIMING_PARAM registers drm/i915/icl: Program TA_TIMING_PARAM registers drm/i915/icl: Get DSI transcoder for a given port drm/i915/icl: Add macros for MMIO of DSI transcoder registers drm/i915/icl: Define TRANS_DSI_FUNC_CONF register drm/i915/icl: Configure DSI transcoders drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers drm/i915/icl: Define DSI transcoder timing registers drm/i915/icl: Configure DSI transcoder timings drm/i915/icl: Define TRANS_CONF register for DSI drm/i915/icl: Enable DSI transcoders drm/i915/icl: Define DSI panel programming registers drm/i915/icl: Set max return packet size for DSI panel drivers/gpu/drm/i915/i915_pci.c | 6 +- drivers/gpu/drm/i915/i915_reg.h | 208 +++++++++++++ drivers/gpu/drm/i915/icl_dsi.c | 567 ++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_display.h | 6 +- drivers/gpu/drm/i915/intel_dsi.h | 7 + drivers/gpu/drm/i915/intel_dsi_vbt.c | 202 +++++++++---- 6 files changed, 934 insertions(+), 62 deletions(-)