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[v13,0/6] Per context dynamic (sub)slice power-gating

Message ID 20180917113058.28994-1-tvrtko.ursulin@linux.intel.com (mailing list archive)
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Series Per context dynamic (sub)slice power-gating | expand

Message

Tvrtko Ursulin Sept. 17, 2018, 11:30 a.m. UTC 
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Fix for Icelake input validation logic and more review feedback.

Lionel Landwerlin (2):
  drm/i915: Record the sseu configuration per-context & engine
  drm/i915/perf: lock powergating configuration to default when active

Tvrtko Ursulin (4):
  drm/i915/execlists: Move RPCS setup to context pin
  drm/i915: Add timeline barrier support
  drm/i915: Expose RPCS (SSEU) configuration to userspace
  drm/i915/icl: Support co-existence between per-context SSEU and OA

 drivers/gpu/drm/i915/i915_drv.h               |  14 +
 drivers/gpu/drm/i915/i915_gem_context.c       | 320 +++++++++++++++++-
 drivers/gpu/drm/i915/i915_gem_context.h       |  10 +
 drivers/gpu/drm/i915/i915_perf.c              |  13 +-
 drivers/gpu/drm/i915/i915_request.c           |  13 +
 drivers/gpu/drm/i915/i915_request.h           |  10 +
 drivers/gpu/drm/i915/i915_timeline.c          |   3 +
 drivers/gpu/drm/i915/i915_timeline.h          |  27 ++
 drivers/gpu/drm/i915/intel_lrc.c              | 100 ++++--
 drivers/gpu/drm/i915/intel_lrc.h              |   2 +
 .../gpu/drm/i915/selftests/mock_timeline.c    |   2 +
 include/uapi/drm/i915_drm.h                   |  43 +++
 12 files changed, 520 insertions(+), 37 deletions(-)